NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1236 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1236 of 1269NXP Semiconductors UM10503Chapter 50: Supplementary informationstructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637Table 513. _USB_OTHER_SPEED_CONFIGURATIONclass structure . . . . . . . . . . . . . . . . . . . . . . . .638Table 514. _USB_SETUP_PACKET class structure . . . .638Table 515. _USB_STRING_DESCRIPTOR classstructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639Table 516. _WB_T class structure. . . . . . . . . . . . . . . . . .639Table 517. USBD_API class structure . . . . . . . . . . . . . . .639Table 518. USBD_API_INIT_PARAM class structure . . .640Table 519. USBD_CDC_API class structure . . . . . . . . . .642Table 520. USBD_CDC_INIT_PARAM class structure . .644Table 521. USBD_CORE_API class structure. . . . . . . . .652Table 522. USBD_DFU_API class structure . . . . . . . . . .656Table 523. USBD_DFU_INIT_PARAM class structure . .657Table 524. USBD_HID_API class structure. . . . . . . . . . .659Table 525. USBD_HID_INIT_PARAM class structure . . .660Table 526. USBD_HW_API class structure . . . . . . . . . . .666Table 527. USBD_MSC_API class structure . . . . . . . . . .674Table 528. USBD_MSC_INIT_PARAM class structure . .675Table 529. Ethernet clocking and power control . . . . . . .679Table 530. Ethernet pin description . . . . . . . . . . . . . . . . .681Table 531. Register overview: Ethernet MAC and DMA (baseaddress 0x4001 0000) . . . . . . . . . . . . . . . . . .682Table 532. MAC Configuration register (MAC_CONFIG,address 0x4001 0000) bit description . . . . . .683Table 533. MAC Frame filter register(MAC_FRAME_FILTER, address 0x4001 0004)bit description . . . . . . . . . . . . . . . . . . . . . . . .686Table 534. MAC Hash table high register(MAC_HASHTABLE_HIGH, address 0x40010008) bit description . . . . . . . . . . . . . . . . . . .688Table 535. MAC Hash table low register(MAC_HASHTABLE_LOW, address 0x40010008) bit description . . . . . . . . . . . . . . . . . . .688Table 536. MAC MII Address register (MAC_MII_ADDR,address 0x4001 0010) bit description . . . . . .689Table 537. CSR clock range values. . . . . . . . . . . . . . . . .689Table 538. MII Data register (MAC_MII_DATA, address0x4001 0014) bit description . . . . . . . . . . . .690Table 539. MAC Flow control register (MAC_FLOW_CTRL,address 0x4001 0018) bit description . . . . . .691Table 540. MAC VLAN tag register (MAC_VLAN_TAG,address 0x4001 01C) bit description . . . . . .692Table 541. MAC Debug register (MAC_DEBUG, address0x4001 0024) bit description . . . . . . . . . . . .693Table 542. MAC Remote wake-up frame filter register(MAC_RWAKE_FRFLT, address 0x4001 0028) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . .694Table 543. MAC PMT control and status register(MAC_PMT_CTRL_STAT, address 0x4001 002C)bit description . . . . . . . . . . . . . . . . . . . . . . . .694Table 544. MAC Interrupt status register (MAC_INTR,address 0x4001 0038) bit description . . . . . .695Table 545. MAC Interrupt mask register (MAC_INTR_MASK,address 0x4001 003C) bit description . . . . .696Table 546. MAC Address 0 high register(MAC_ADDR0_HIGH, address 0x4001 0040) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . .697Table 547. MAC Address 0 low register(MAC_ADDR0_LOW, address 0x4001 0044) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 697Table 548. MAC IEEE1588 time stamp control register(MAC_TIMESTP_CTRL, address 0x4001 0700)bit description . . . . . . . . . . . . . . . . . . . . . . . . 698Table 549. Time stamp snapshot dependency on registerbits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699Table 550. Sub-second increment register(SUBSECOND_INCR, address 0x4001 0704) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 700Table 551. System time seconds register (SECONDS,address 0x4001 0708) bit description . . . . . 700Table 552. System time nanoseconds register(NANOSECONDS, address 0x4001 070C) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 701Table 553. System time seconds update register(SECONDSUPDATE, address 0x4001 0710) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 701Table 554. System time nanoseconds update register(NANOSECONDSUPDATE, address 0x40010714) bit description . . . . . . . . . . . . . . . . . . . 702Table 555. Time stamp addend register (ADDEND, address0x4001 0718) bit description . . . . . . . . . . . . 702Table 556. Target time seconds register(TARGETSECONDS, address 0x4001 071C) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 702Table 557. Target time nanoseconds register(TARGETNANOSECONDS, address 0x40010720) bit description . . . . . . . . . . . . . . . . . . . 703Table 558. System time higher words seconds register(HIGHWORD, address 0x4001 0724) bitdescription . . . . . . . . . . . . . . . . . . . . . . . . . . 703Table 559. Time stamp status register (TIMESTAMPSTAT,address 0x4001 0728) bit description . . . . . 704Table 560. DMA Bus mode register (DMA_BUS_MODE,address 0x4001 1000) bit description . . . . . 704Table 561. Programmable burst length settings . . . . . . 706Table 562. DMA Transmit poll demand register(DMA_TRANS_POLL_DEMAND, address0x4001 1004) bit description . . . . . . . . . . . . 706Table 563. DMA Receive poll demand register(DMA_REC_POLL_DEMAND, address 0x40011008) bit description . . . . . . . . . . . . . . . . . . . 707Table 564. DMA Receive descriptor list address register(DMA_REC_DES_ADDR, address 0x4001 100C)bit description . . . . . . . . . . . . . . . . . . . . . . . . 707Table 565. DMA Transmit descriptor list address register(DMA_TRANS_DES_ADDR, address 0x40011010) bit description . . . . . . . . . . . . . . . . . . . 708Table 566. DMA Status register (DMA_STAT, address0x4001 1014) bit description . . . . . . . . . . . . 708Table 567. DMA operation mode register (DMA_OP_MODE,address 0x4001 1018) bit description . . . . . 711Table 568. DMA Interrupt enable register (DMA_INT_EN,address 0x4001 101C) bit description . . . . . 713Table 569. DMA Missed frame and buffer overflow counterregister (DMA_MFRM_BUFOF, address 0x4001