NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 607 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 607 of 1269NXP Semiconductors UM10503Chapter 24: LPC43xx USB1 Host/Device controllerUpon discovery of a transmit (OUT/SETUP) packet in the data structures, host controllerchecks to ensure T p remains before the end of the (micro) frame. If so it proceeds topre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the[micro]frame is < Ts then the packet attempt ceases and the packet is tried at a later time.Although this is not an error condition and the host controller will eventually recover, amark will be made the scheduler health counter to note the occurrence of a “backoff”event. When a back-off event is detected, the partial packet fetched may need to bediscarded from the latency buffer to make room for periodic traffic that will begin after thenext SOF. Too many back-off events can waste bandwidth and power on the system busand thus should be minimized (not necessarily eliminated). Backoffs can be minimizedwith use of the TSCHHEALTH (T ff) described below.24.6.11 USB ULPI viewport register (ULPIVIEWPORT)The register provides indirect access to the ULPI PHY register set. Although the coreperforms access to the ULPI PHY register set, there may be extraordinary circumstanceswhere software may need direct access.Table 476. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 7164) bitdescriptionBit Symbol Description ResetvalueAccess7:0 TXSCHOH FIFO burst thresholdThis register controls the number of data bursts that are posted to the TXlatency FIFO in host mode before the packet begins on to the bus. Theminimum value is 2 and this value should be a low as possible to maximizeUSB performance. A higher value can be used in systems with unpredictablelatency and/or insufficient bandwidth where the FIFO may underrun becausethe data transferred from the latency FIFO to USB occurs before it can bereplenished from system memory. This value is ignored if the Stream Disablebit in USBMODE register is set.0x2 R/W12:8 TXSCHEATLTH Scheduler health counterThis register increments when the host controller fails to fill the TX latencyFIFO to the level programmed by TXFIFOTHRES before running out of timeto send the packet before the next Start-Of-Frame .This health counter measures the number of times this occurs to providefeedback to selecting a proper TXSCHOH. Writing to this register will clear thecounter. The maximum value is 31.0x0 R/W15:13 - Reserved - -21:16 TXFIFOTHRES Scheduler overheadThis register adds an additional fixed offset to the schedule time estimatordescribed above as Tff. As an approximation, the value chosen for this registershould limit the number of back-off events captured in the TXSCHHEALTH toless than 10 per second in a highly utilized bus. Choosing a value that is toohigh for this register is not desired as it can needlessly reduce USB utilization.The time unit represented in this register is 1.267 s when a device isconnected in High-Speed Mode.The time unit represented in this register is 6.333 s when a device isconnected in Low/Full Speed Mode.0x0 R/W31:22 - Reserved