NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 956 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 956 of 1269NXP Semiconductors UM10503Chapter 37: LPC43xx USART0_2_3If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If theIntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify thetype of interrupt and handling as described in Table 828. Given the status of IIR[3:0], aninterrupt handler routine can determine the cause of the interrupt and how to clear theactive interrupt. The IIR must be read in order to clear the interrupt prior to exiting theInterrupt Service Routine.The USART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is setwhenever any one of four error conditions occur on the USART RX input: overrun error(OE), parity error (PE), framing error (FE) and break interrupt (BI). The USART Rx errorcondition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upona LSR read.The USART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTIinterrupt (IIR[3:1] = 110). The RDA is activated when the USART Rx FIFO reaches thetrigger level defined in FCR7:6 and is reset when the USART Rx FIFO depth falls belowthe trigger level. When the RDA interrupt goes active, the CPU can read a block of datadefined by the trigger level.The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the USARTRx FIFO contains at least one character and no USART Rx FIFO activity has occurred in3.5 to 4.5 character times. Any USART Rx FIFO activity (read or write of USART RSR) willclear the interrupt. This interrupt is intended to flush the USART RBR after a message hasbeen received that is not a multiple of the trigger level size. For example, if a peripheralwished to send a 105 character message and the trigger level was 10 characters, theCPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5CTI interrupts (depending on the service routine) resulting in the transfer of the remaining5 characters.Table 828. USART Interrupt HandlingIIR[3:0]value[1]Priority InterrupttypeInterrupt source Interruptreset0001 - None None -0110 Highest RX LineStatus /ErrorOE[2] or PE [2] or FE[2] or BI [2] LSR Read[2]