NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 91 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 91 of 1269NXP Semiconductors UM10503Chapter 10: LPC43xx Power Management Controller (PMC)10.2.6 Memory retention in Power-down modesTable 57 shows which parts of the SRAM memory are preserved in Sleep mode and thevarious power-down modes.In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN,Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not inPower-down mode and Deep-power-down mode.[1] 64 kB for LPC4350/30; 32 kB for LPC4320/10 and parts with on-chip flash[2] For LPC4350/30 starting at 0x1009 0000; for LPC4320/10 and parts with on-chip flash starting at 0x1008 8000.10.3 Register descriptionTable 57. Memory retentionMode 128 kB localSRAM startingat 0x1000 000064/32 kB LocalSRAM starting at0x1008 0000[1]8 kB local SRAMstarting at0x1009 0000/0x1008 8000[2]64 kB AHB SRAMstarting at0x2000 0000256 byte backupregisters at0x4004 1000(RTC powerdomain)Sleep mode yes yes yes yes yesDeep-sleep mode yes yes yes yes yesPower-down mode no no yes no yesDeep power-downmodeno no no no yesTable 58. Register overview: Power Mode Controller (PMC) (base address 0x4004 2000)Name Access AddressoffsetDescription ResetvalueReferencePD0_SLEEP0_HW_ENA R/W 0x000 Hardware sleep eventenable register0x00000001Table 59- - 0x004 -0x018Reserved - -PD0_SLEEP0_MODE R/W 0x01C Power-down modecontrol register0x003FFF7FTable 60