NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1037 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1037 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interface41.6.5 I2S Status Feedback registerThe STATE register provides status information about the I2S interface.41.6.6 I2S DMA Configuration Register 1The DMA1 register controls the operation of DMA request 1. The function of bits in DMA1are shown in Table 903. Refer to Chapter 19 for details of DMA operation.This register enables the DMA for the I 2 S receive and transmit channels and sets theFIFO level.Remark: The FIFOs contain eight 32 bit Dwords. Therefore, if the I 2S controller isconfigured for 32-bit mode (see Table 898 and Table 899), the maximum allowed FIFOlevel is 4.Table 901. I2S Receive FIFO register (RXFIFO - address 0x400A 200C (I2S0) and 0x400A 300C (I2S1)) bit descriptionBit Symbol Description Reset value31:0 I2SRXFIFO 8 x 32-bit transmit FIFO. 0Table 902. I2S Status Feedback register (STATE - address 0x400A 2010 (I2S0) and 0x400A 3010 (I2S1)) bitdescriptionBit Symbol Description Resetvalue0 IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determinedby comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQregister.11 DMAREQ1 This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined bycomparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in theDMA1 register.12 DMAREQ2 This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined bycomparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in theDMA2 register.17:3 - Reserved. 011:8 RX_LEVEL Reflects the current level of the Receive FIFO. 015:12 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.-19:16 TX_LEVEL Reflects the current level of the Transmit FIFO. 031:20 - Reserved, user software should not write ones to reserved bits. The value read from areserved bit is not defined.-Table 903. I2S DMA Configuration register 1 (DMA1 - address 0x400A 2014 (I2S0) and 0x400A 3014 (I2S1)) bitdescriptionBit Symbol Description Resetvalue0 RX_DMA1_ENABLE When 1, enables DMA1 for I2S receive. 01 TX_DMA1_ENABLE When 1, enables DMA1 for I2S transmit. 07:2 - Reserved, user software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.011:8 RX_DEPTH_DMA1 Set the FIFO level that triggers a receive DMA request on DMA1. 0