NXP Semiconductors LPC43 Series User Manual
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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 827 of 1269NXP Semiconductors UM10503Chapter 28: LPC43xx State Configurable Timer (SCT)5:4 O2RES Effect of simultaneous set and clear on output 2. 00x0 No change.0x1 Set output (or clear based on the SETCLR2 field).0x2 Clear output n (or set based on the SETCLR2 field).0x3 Toggle output.7:6 O3RES Effect of simultaneous set and clear on output 3. 00x0 No change.0x1 Set output (or clear based on the SETCLR3 field).0x2 Clear output (or set based on the SETCLR3 field).0x3 Toggle output.9:8 O4RES Effect of simultaneous set and clear on output 4. 00x0 No change.0x1 Set output (or clear based on the SETCLR4 field).0x2 Clear output (or set based on the SETCLR4 field).0x3 Toggle output.11:10O5RES Effect of simultaneous set and clear on output 5. 00x0 No change.0x1 Set output (or clear based on the SETCLR5 field).0x2 Clear output (or set based on the SETCLR5 field).0x3 Toggle output.13:12O6RES Effect of simultaneous set and clear on output 6. 00x0 No change.0x1 Set output (or clear based on the SETCLR6 field).0x2 Clear output (or set based on the SETCLR6 field).0x3 Toggle output.15:14O7RES Effect of simultaneous set and clear on output 7. 00x0 No change.0x1 Set output (or clear based on the SETCLR7 field).0x2 Clear output (or set based on the SETCLR7 field).0x3 Toggle output.17:16O8RES Effect of simultaneous set and clear on output 8. 00x0 No change.0x1 Set output (or clear based on the SETCLR8 field).0x2 Clear output (or set based on the SETCLR8 field).0x3 Toggle output.19:18O9RES Effect of simultaneous set and clear on output 9. 00x0 No change.0x1 Set output (or clear based on the SETCLR9 field).0x2 Clear output (or set based on the SETCLR9 field).0x3 Toggle output.Table 659. SCT conflict resolution register (RES - address 0x4000 0058) bit descriptionBit Symbol Value Description Resetvalue |
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