NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 840 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 840 of 1269NXP Semiconductors UM10503Chapter 28: LPC43xx State Configurable Timer (SCT)28.7.10 SCT operationIn its simplest, single-state configuration, the SCT operates as an event controlled one- orbidirectional counter. Events can be configured to be counter match events, an input oroutput level, transitions on an input or output pin, or a combination of match andinput/output behavior. In response to an event, the SCT output or outputs can transition,or the SCT can perform other actions such as creating an interrupt or starting, stopping, orresetting the counter. Multiple simultaneous actions are allowed for each event.Furthermore, any number of events can trigger one specific action of the SCT.An action or multiple actions of the SCT uniquely define an event. A state is defined bywhich events are enabled to trigger an SCT action or actions in any stage of the counter.Events not selected for this state are ignored.In a multi-state configuration, states change in response to events. A state change is anadditional action that the SCT can perform when the event occurs. When an event isconfigured to change the state, the new state defines a new set of events resulting indifferent actions of the SCT. Through multiple cycles of the counter, events can changethe state multiple times and thus create a large variety of event controlled transitions onthe SCT outputs and/or interrupts.Once configured, the SCT can run continuously without software intervention and cangenerate multiple output patterns entirely under the control of events.• To configure the SCT, see Section 28.7.10.1.• To start, run, and stop the SCT, see Section 28.7.10.2.• To configure the SCT as simple event controlled counter/timer, see Section 28.7.10.3.28.7.10.1 Configure the SCTTo set up the SCT for multiple events and states, perform the following configurationsteps:28.7.10.1.1 Configure the counter1. Configure the L and H counters in the CONFIG register by selecting two independent16-bit counters (L counter and H counter) or one combined 32-bit counter in theUNIFY field.2. Select the SCT clock source in the CONFIG register (fields CLKMODE and CLKSEL)from any of the inputs or an internal clock.28.7.10.1.2 Configure the match and capture registers1. Select how many match and capture registers the application uses (total of up to 16):– In the REGMODE register, select for each of the 16 match/capture register pairswhether the register is used as a match register or capture register.2. Define match conditions for each match register selected:– Each match register MATCH sets one match value, if a 32-bit counter is used, ortwo match values, if the L and H 16-bit counters are used.– Each match reload register MATCHRELOAD sets a reload value that is loaded intothe match register when the counter reaches a limit condition or the value 0.