UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 235 of 1269NXP Semiconductors UM10503Chapter 14: LPC43xx Pin configurationP1_18 N12 N10 95 [3] N;PUI/O GPIO0[13] — General purpose digital input/output pin.I/O U2_DIR — RS-485/EIA-485 output enable/direction control forUSART2.- R — Function reserved.O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).O T0_MAT3 — Match output 3 of timer 0.I CAN1_RD — CAN1 receiver input.I/O SGPIO12 — General purpose digital input/output pin.I/O EMC_D10 — External memory data line 10.P1_19 M11 N9 96 [3] N;PUI ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit Clock (MIIinterface) or Ethernet Reference Clock (RMII interface).I/O SSP1_SCK — Serial clock for SSP1.- R — Function reserved.- R — Function reserved.O CLKOUT — Clock output pin.- R — Function reserved.O I2S0_RX_MCLK — I2S receive master clock.I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master andreceived by the slave. Corresponds to the signal SCK in the I 2S-busspecification.P1_20 M10 J10 100 [3] N;PUI/O GPIO0[15] — General purpose digital input/output pin.I/O SSP1_SSEL — Slave Select for SSP1.- R — Function reserved.O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).I T0_CAP2 — Capture input 2 of timer 0.- R — Function reserved.I/O SGPIO13 — General purpose digital input/output pin.I/O EMC_D11 — External memory data line 11.Table 130. LPC4357/53 Pin description …continuedPin nameLBGA256TFBGA180LQFP208Reset state[2]TypeDescription