NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 104 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 104 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.6.1 Frequency monitor registerThe CGU can report the relative frequency of any operating clock. The clock to bemeasured must be selected by software, while the fixed-frequency IRC clock fref is usedas the reference frequency. A 14-bit counter then counts the number of cycles of themeasured clock that occur during a user-defined number of reference-clock cycles. Whenthe MEAS bit is set, the measured-clock counter is reset to 0 and counts up, while the9-bit reference-clock counter is loaded with the value in RCNT and then counts downtowards 0. When either counter reaches its terminal value both counters are disabled andthe MEAS bit is reset to 0. The current values of the counters can then be read out andthe selected frequency obtained by the following equation:Note that the accuracy of this measurement can be affected by several factors:1. Quantization error is noticeable if the ratio between the two clocks is large (e.g.100 kHz vs. 1 kHz), because one counter saturates while the other still has only asmall count value.2. Due to synchronization, the counters are not started and stopped at exactly the sametime.3. The measured frequency can only be to the same level of precision as the referencefrequency.OUTCLK_21_CTRLtoOUTCLK_24_CTRLR/W 0x0B0 to0x0BCReserved output stages - - - -BASE_APLL_CLK R/W 0x0C0 Output stage 25 controlregister for base clockBASE_APLL_CLK0x010000000x010000000x01000000Table 90BASE_CGU_OUT0_CLKR/W 0x0C4 Output stage 26 controlregister for base clockBASE_CGU_OUT0_CLK0x010000000x010000000x01000000Table 91BASE_CGU_OUT1_CLKR/W 0x0C8 Output stage 27 controlregister for base clockBASE_CGU_OUT1_CLK0x010000000x010000000x01000000Table 91Table 67. Register overview: CGU (base address 0x4005 0000)Name Access AddressoffsetDescription ResetvalueResetvalueafterEMC,UART0/3 bootResetvalueafterUSB0/1bootReferencefselected FCNTRCNT---------------- fref=