NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 960 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 960 of 1269NXP Semiconductors UM10503Chapter 37: LPC43xx USART0_2_3Table 831. USART Line Status Register Read Only (LSR - addresses 0x4008 1014 (USART0),0x400C 1014 (USART2), 0x400C 2014 (USART3)) bit descriptionBit Symbol Value Description ResetValue0 RDR Receiver Data Ready.LSR[0] is set when the RBR holds an unread character and iscleared when the USART RBR FIFO is empty.00 RBR is empty.1 RBR contains valid data.1 OE Overrun Error.The overrun error condition is set as soon as it occurs. A LSRread clears LSR[1]. LSR[1] is set when USART RSR has a newcharacter assembled and the USART RBR FIFO is full. In thiscase, the USART RBR FIFO will not be overwritten and thecharacter in the USART RSR will be lost.00 Overrun error status is inactive.1 Overrun error status is active.2 PE Parity Error.When the parity bit of a received character is in the wrong state, aparity error occurs. A LSR read clears LSR[2]. Time of parity errordetection is dependent on FCR[0].Note: A parity error is associated with the character at the top ofthe USART RBR FIFO.00 Parity error status is inactive.1 Parity error status is active.3 FE Framing Error.When the stop bit of a received character is a logic 0, a framingerror occurs. A LSR read clears LSR[3]. The time of the framingerror detection is dependent on FCR0. Upon detection of aframing error, the RX will attempt to re-synchronize to the dataand assume that the bad stop bit is actually an early start bit.However, it cannot be assumed that the next received byte will becorrect even if there is no Framing Error.Note: A framing error is associated with the character at the topof the USART RBR FIFO.00 Framing error status is inactive.1 Framing error status is active.4 BI Break Interrupt.When RXD1 is held in the spacing state (all zeros) for one fullcharacter transmission (start, data, parity, stop), a break interruptoccurs. Once the break condition has been detected, the receivergoes idle until RXD1 goes to marking state (all ones). A LSR readclears this status bit. The time of break detection is dependent onFCR[0].Note: The break interrupt is associated with the character at thetop of the USART RBR FIFO.00 Break interrupt status is inactive.1 Break interrupt status is active.