NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 989 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 989 of 1269NXP Semiconductors UM10503Chapter 38: LPC43xx UART1Bit IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baudcondition. The auto-baud interrupt conditions are cleared by setting the correspondingClear bits in the Auto-baud Control Register.If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatusis 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type ofinterrupt and handling as described in Table 855. Given the status of IIR[3:0], an interrupthandler routine can determine the cause of the interrupt and how to clear the activeinterrupt. The IIR must be read in order to clear the interrupt prior to exiting the InterruptService Routine.The UART1 RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is setwhenever any one of four error conditions occur on the UART1RX input: overrun error(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART1 Rx errorcondition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared uponan LSR read.The UART1 RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTIinterrupt (IIR[3:1] = 110). The RDA is activated when the UART1 Rx FIFO reaches thetrigger level defined in FCR7:6 and is reset when the UART1 Rx FIFO depth falls belowthe trigger level. When the RDA interrupt goes active, the CPU can read a block of datadefined by the trigger level.The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART1Rx FIFO contains at least one character and no UART1 Rx FIFO activity has occurred in3.5 to 4.5 character times. Any UART1 Rx FIFO activity (read or write of UART1 RSR) willclear the interrupt. This interrupt is intended to flush the UART1 RBR after a message hasbeen received that is not a multiple of the trigger level size. For example, if a peripheralwished to send a 105 character message and the trigger level was 10 characters, theCPU would receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5CTI interrupts (depending on the service routine) resulting in the transfer of the remaining5 characters.8 ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully andinterrupt is enabled.09 ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt isenabled.031:10 - Reserved, the value read from a reserved bit is not defined. NATable 854: UART1 Interrupt Identification Register (IIR - address 0x4008 2008) bit descriptionBit Symbol Value Description ResetvalueTable 855: UART1 Interrupt HandlingIIR[3:0]value[1]Priority InterruptTypeInterrupt Source Interrupt Reset0001 - None None -0110 Highest RX LineStatus /ErrorOE[2] or PE[2] or FE[2] or BI[2] LSR Read[2]0100 Second RX DataAvailableRx data available or trigger level reached in FIFO(FCR0=1)RBR Read[3] or UART1 FIFOdrops below trigger level