NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 698 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 698 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx EthernetTable 548. MAC IEEE1588 time stamp control register (MAC_TIMESTP_CTRL, address 0x4001 0700) bit descriptionBit Symbol Description ResetvalueAccess0 TSENA Time Stamp EnableWhen this bit, is set the timestamping is enabled for transmit and receiveframes. When disabled timestamp is not added for transmit and receiveframes and the TimeStamp Generator is also suspended. User has to alwaysinitialize the TimeStamp (system time) after enabling this mode.0 R/W1 TSCFUPDT Time Stamp Fine or Coarse UpdateWhen set, indicates that the system times update to be done using fineupdate method. When reset it indicates the system time stamp update to bedone using Coarse method. This bit is reserved if the fine correction option isnot enabled.0 R/W2 TSINIT Time Stamp InitializeThis register field can be read and written by the application (Read andWrite), and is cleared to 0 by the Ethernet core (Self Clear).When set, the system time is initialized (over-written) with the value specifiedin the Time Stamp High Update and Time Stamp Low Update registers. Thisregister bit should be read zero before updating it. This bit is reset once theinitialize is complete.0 R/W3 TSUPDT Time Stamp UpdateThis register field can be read and written by the application (Read andWrite), and is cleared to 0 by the Ethernet core (Self Clear).When set, the system time is updated (added/subtracted) with the valuespecified in the Time Stamp High Update and Time Stamp Low Updateregisters. This register bit should be read zero before updating it. This bit isreset once the update is completed in hardware.0 R/W4 TSTRIG Time Stamp Interrupt Trigger EnableThis register field can be read and written by the application (Read andWrite), and is cleared to 0 by the Ethernet core (Self Clear).When set, the Time Stamp interrupt is generated when the System Timebecomes greater than the value written in Target Time register. This bit isreset after the generation of Time Stamp Trigger Interrupt.0 R/W5 TSADDREG Addend Reg UpdateWhen set, the contents of the Time Stamp Addend register is updated in thePTP block for fine correction. This is cleared when the update is completed.This register bit should be zero before setting it. This is a reserved bit whenonly coarse correction option is selected.7:6 - Reserved8 TSENALL Enable Time Stamp for All FramesWhen set, the time stamp snapshot is enabled for all frames received by thecore.0 R/W9 TSCTRLSSR Time Stamp Digital or Binary rollover controlWhen set, the Time Stamp Low register rolls over after 0x3B9A_C9FF value(i.e., 1 nanosecond accuracy) and increments the Time Stamp (High)seconds. When reset, the rollover value of sub-second register is0x7FFF_FFFF. The sub-second increment has to be programmed correctlydepending on the PTP reference clock frequency and this bit value.0 R/W10 TSVER2ENA Enable PTP packet snooping for version 2 formatWhen set, the PTP packets are snooped using the 1588 version 2 formatelse snooped using the version 1 format.0 R/W