NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 976 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 976 of 1269NXP Semiconductors UM10503Chapter 37: LPC43xx USART0_2_3The USART master transmitter will identify an address character by setting the parity (9th)bit to ‘1’. For data characters, the parity bit is set to ‘0’.Each USART slave receiver can be assigned a unique address. The slave can beprogrammed to either manually or automatically reject data following an address which isnot theirs.RS-485/EIA-485 Normal Multidrop Mode (NMM)Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detectedwhen a received byte causes the USART to set the parity error and generate an interrupt.If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received data bytes will be ignoredand will not be stored in the RXFIFO. When an address byte is detected (parity bit = ‘1’) itwill be placed into the RXFIFO and an Rx Data Ready Interrupt will be generated. Theprocessor can then read the address byte and decide whether or not to enable thereceiver to accept the following data.While the receiver is enabled (RS485CTRL bit 1 =’0’), all received bytes will be acceptedand stored in the RXFIFO regardless of whether they are data or address. When anaddress character is received a parity error interrupt will be generated and the processorcan decide whether or not to disable the receiver.RS-485/EIA-485 Auto Address Detection (AAD) modeWhen both RS485CTRL register bits 0 (9-bit mode enable) and 2 (AAD mode enable) areset, the USART is in auto address detect mode.In this mode, the receiver will compare any address byte received (parity = ‘1’) to the 8-bitvalue programmed into the RS485ADRMATCH register.If the receiver is disabled (RS485CTRL bit 1 = ‘1’), any received byte will be discarded if itis either a data byte OR an address byte which fails to match the RS485ADRMATCHvalue.When a matching address character is detected it will be pushed onto the RXFIFO alongwith the parity bit, and the receiver will be automatically enabled (RS485CTRL bit 1 will becleared by hardware). The receiver will also generate an Rx Data Ready Interrupt.While the receiver is enabled (RS485CTRL bit 1 = ‘0’), all bytes received will be acceptedand stored in the RXFIFO until an address byte which does not match theRS485ADRMATCH value is received. When this occurs, the receiver will be automaticallydisabled in hardware (RS485CTRL bit 1 will be set), The received non-matching addresscharacter will not be stored in the RXFIFO.RS-485/EIA-485 Auto Direction ControlRS485/EIA-485 mode includes the option of allowing the transmitter to automaticallycontrol the state of the DIR pin as a direction control output signal.Setting RS485CTRL bit 4 = ‘1’ enables this feature.When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW)when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH)once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRLregister.