NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1051 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1051 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interface41.7.2.1.7 Transmitter master mode (External MCLK)Table 918. Transmitter master mode (External MCLK)CREG bit 12 DAO bit 5 TXMODEbits [3:0]Description0 0 0 0 0 1 Transmitter master mode.The I2S transmit function operates as a master.The transmit clock source (TX_MCLK) is provided by the external master on theTX_MCLK pin.The WS used is the internally generated TX_WS.The TX_MCLK pin is enabled for input.Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select PLL0AUDIO for the I2S0 interface. CREGbits 14 and 15 select PLL0AUDIO for the I2S1 interface.Fig 141. Transmitter master mode (External MCLK)I 2 SperipheralblockI2STXMODE[1:0]=01 I2STXMODE[2]=001TX_SCKRX_SCK(1 to 64)TX_MCLK 10008-bitFractionalRate DividerX YI2STX_RATE[15:8]I2STX_RATE[7:0]10I2STXBITRATE[5:0]RX_MCLK01TX_WSRX_WSI2SDAO[5]=0 Pin OEnI2S_TX_WSI2S_TX_SDAI2S_TX_MCLKI2STXMODE[3]=0 Pin OEI2S_TX_SCK01I2SDAO[5]=001CREG6[12]=001PLLAUDIOI2STXMODE[2]=0PCLK