NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 692 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 692 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx Ethernet26.6.8 MAC VLAN tag registerThe VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames.The MAC compares the 13th and 14th bytes of the receiving frame (Length/Type) with0x8100, and the following 2 bytes are compared with the VLAN tag; if a match occurs, itsets the received VLAN bit in the receive frame status. The legal length of the frame isincreased from 1518 bytes to 1522 bytes.If the VLAN Tag register is configured to be double-synchronized to the MII clock domain,then consecutive writes to these register should be performed only after at least 4 clockcycles in the destination clock domain.26.6.9 MAC Debug registerThis debug register gives the status of all the main modules of the transmit and receivedata-paths and the FIFOs. An all-zero status indicates that the MAC core is in idle state(and FIFOs are empty) and no activity is going on in the data-paths.7 DZPQ Disable Zero-Quanta PauseWhen set, this bit disables the automatic generation of Zero-Quanta Pause Controlframes on the deassertion of the flow-control signal from the FIFO layer. When this bitis reset, normal operation with automatic Zero-Quanta Pause Control framegeneration is enabled.0 R/W15:8 - Reserved 0 RO31:16 PT Pause timeThis field holds the value to be used in the Pause Time field in the transmit controlframe. If the Pause Time bits is configured to be double-synchronized to the MII clockdomain, then consecutive writes to this register should be performed only after atleast 4 clock cycles in the destination clock domain.0x0000R/WTable 539. MAC Flow control register (MAC_FLOW_CTRL, address 0x4001 0018) bit description …continuedBit Symbol Description ResetvalueAccessTable 540. MAC VLAN tag register (MAC_VLAN_TAG, address 0x4001 01C) bit descriptionBit Symbol Description ResetvalueAccess15:0 VL VLAN Tag Identifier for Receive FramesThis contains the 802.1Q VLAN tag to identify VLAN frames, and is compared to thefifteenth and sixteenth bytes of the frames being received for VLAN frames.Bits[15:13] are the User Priority, Bit[12] is the Canonical Format Indicator (CFI) andbits[11:0] are the VLAN tag’s VLAN Identifier (VID) field. When the ETV bit is set, onlythe VID (Bits[11:0]) is used for comparison.If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth andsixteenth bytes for VLAN tag comparison, and declares all frames with a Type fieldvalue of 0x8100 to be VLAN frames.0x0000R/W16 ETV Enable 12-Bit VLAN Tag ComparisonWhen this bit is set, a 12-bit VLAN identifier, rather than the complete 16-bit VLANtag, is used for comparison and filtering. Bits[11:0] of the VLAN tag are compared withthe corresponding field in the received VLAN-tagged frame.When this bit is reset, all 16 bits of the received VLAN frame’s fifteenth and sixteenthbytes are used for comparison.0 R/W31:17 - Reserved 0x0000RO