NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 963 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 963 of 1269NXP Semiconductors UM10503Chapter 37: LPC43xx USART0_2_3The PulseDiv bits in U3ICR are used to select the pulse width when the fixed pulse widthmode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bitsshould be set so that the resulting pulse width is at least 1.63 μs. Table 835 shows thepossible pulse widths.37.6.12 USART Fractional Divider RegisterThe USART Fractional Divider Register (FDR) controls the clock pre-scaler for the baudrate generation and can be read and written at the user’s discretion. This pre-scaler takesthe APB clock and generates an output clock according to the specified fractionalrequirements.Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value ofthe DLL register must be 3 or greater.1 IRDAINV Serial input direction. 00 The serial input is not inverted.1 The serial input is inverted. This has no effect on theserial output.2 FIXPULSEEN IrDA fixed pulse width mode. 00 IrDA fixed pulse width mode disabled.1 IrDA fixed pulse width mode enabled.5:3 PULSEDIV Configures the pulse when FixPulseEn = 1. SeeTable 835 for details.031:6 - NA Reserved, user software should not write ones toreserved bits. The value read from a reserved bit is notdefined.0Table 835. IrDA Pulse WidthFixPulseEn PulseDiv IrDA Transmitter Pulse width (μs)0 x 3 / (16  baud rate)1 0 2  TPCLK1 1 4  TPCLK1 2 8  TPCLK1 3 16  T PCLK1 4 32  T PCLK1 5 64  T PCLK1 6 128  T PCLK1 7 256  T PCLKTable 834. IrDA Control Register (ICR - address 0x4000 8024) bit descriptionBit Symbol Value Description Resetvalue