NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 874 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 874 of 1269NXP Semiconductors UM10503Chapter 30: LPC43xx Motor Control PWM (MOTOCONPWM)If the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, the match betweenTC and LIM switches the channel’s A output from “active” to “passive” state. If thechannel’s CENTER and DTE bits in CON are both 0, the match simultaneously switchesthe channel’s B output from “passive” to “active” state.If the channel’s CENTER bit is 0 but the DTE bit is 1, the match triggers the channel’sdeadtime counter to begin counting -- when the deadtime counter expires, the channel’s Boutput switches from “passive” to “active” state.In center-aligned mode, matches between a channel’s TC and LIM registers have noeffect on its A and B outputs.Writing to either a Limit or a Match (30.7.5) register loads a “write” register, and if thechannel is stopped it also loads an “operating” register that is compared to the TC. If thechannel is running and its “disable update” bit in CON is 0, the operating registers areloaded from the write registers: 1) in edge-aligned mode, when the TC matches theoperating Limit register; 2) in center-aligned mode, when the TC counts back down to 0. Ifthe channel is running and the “disable update” bit is 1, the operating registers are notloaded from the write registers until software stops the channel.Reading an LIM address always returns the operating value.Remark: In timer mode, the period of a channel’s modulated MCO outputs is determinedby its Limit register, and the pulse width at the start of the period is determined by itsMatch register. If it suits your way of thinking, consider the Limit register to be the “Periodregister” and the Match register to be the “Pulse Width register”.30.7.5 MCPWM Match 0-2 registersThese registers also have “write” and “operating” versions as described above for theLimit registers, and the operating registers are also compared to the channels’ TCs. See30.7.4 above for details of reading and writing both Limit and Match registers.The Match and Limit registers control the MCO0-2 outputs. If a Match register is to haveany effect on its channel’s operation, it must contain a smaller value than thecorresponding Limit register.30.7.5.1 Match register in Edge-Aligned modeIf the channel’s CENTER bit in CON is 0 selecting edge-aligned mode, a match betweenTC and MAT switches the channel’s B output from “active” to “passive” state. If thechannel’s CENTER and DTE bits in CON are both 0, the match simultaneously switchesthe channel’s A output from “passive” to “active” state.Table 706. MCPWM Limit 0 to 2 registers (LIM - 0x400A 0024 (LIM0), 0x400A 0028 (LIM1),0x400A 002C (LIM2)) bit descriptionBit Symbol Description Reset value31:0 MCLIM Limit value. 0xFFFF FFFFTable 707. MCPWM Match 0 to 2 registers (MAT - addresses 0x400A 0030 (MAT0),0x400A 0034 (MAT1), 0x400A 0038 (MAT2)) bit descriptionBit Symbol Description Reset value31:0 MCMAT Match value. 0xFFFF FFFF