NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 474 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 474 of 1269NXP Semiconductors UM10503Chapter 21: LPC43xx External Memory Controller (EMC)[1] The external memory cannot be accessed in low-power or disabled state. If a memory access is performedan AHB error response is generated. The EMC registers can be programmed in low-power and/or disabledstate.21.7.2 EMC Status registerThe read-only Status register provides EMC status information.Table 354. EMC Control register (CONTROL - address 0x4000 5000) bit descriptionBit Symbol Value Description Resetvalue0 E EMC Enable. Indicates if the EMC is enabled ordisabled.Disabling the EMC reduces power consumption. Whenthe memory controller is disabled the memory is not refreshed.The memory controller is enabled by setting the enable bit, or byreset. This bit must only be modified when the EMC is in idlestate. [1]10 Disabled1 Enabled (POR and warm reset value).1 M Address mirror. Indicates normal or reset memory map. On POR,CS1 is mirrored to both CS0 and DYCS0 memory areas.Clearing the M bit enables CS0 and DYCS0 memory to beaccessed.10 Normal memory map.1 Reset memory map. Static memory CS1 is mirrored onto CS0and DYCS0 (POR reset value).2 L Low-power mode. Indicates normal, or low-power mode.Entering low-power mode reduces memory controller powerconsumption. Dynamic memory is refreshed as necessary. Thememory controller returns to normal functional mode by clearingthe low-power mode bit (L), or by POR.This bit must only be modified when the EMC is in idle state. [1]00 Normal mode (warm reset value).1 Low-power mode.31:3 - - Reserved, user software should not write ones to reserved bits.The value read from a reserved bit is not defined.-Table 355. EMC Status register (STATUS - address 0x4000 5004) bit descriptionBit Symbol Value Description Resetvalue0 B Busy.This bit is used to ensure that the memory controller entersthe low-power or disabled mode cleanly by determining ifthe memory controller is busy or not:10 EMC is idle (warm reset value).1 EMC is busy performing memory transactions, commands,auto-refresh cycles, or is in self-refresh mode (POR resetvalue).1 S Write buffer status. This bit enables the EMC to enterlow-power mode or disabled mode cleanly:00 Write buffers empty (POR reset value)1 Write buffers contain data.