NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 917 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 917 of 1269NXP Semiconductors UM10503Chapter 33: LPC43xx Alarm timer33.4.4 Interrupt set enable register33.4.5 Interrupt status register33.4.6 Interrupt enable register33.4.7 Clear status register33.4.8 Set status registerTable 766. Interrupt set enable register (SET_EN - 0x4004 0FDC) bit descriptionBit Symbol Description Reset value0 SET_EN Writing a 1 to this bit sets the interrupt enable bit in theENABLE register.031:1 - Reserved. -Table 767. Interrupt status register (STATUS - 0x4004 0FE0) bit descriptionBit Symbol Description Reset value0 STAT A 1 in this bit shows that the STATUS interrupt has beenraised.031:1 - Reserved. -Table 768. Interrupt enable register (ENABLE - 0x4004 0FE4) bit descriptionBit Symbol Description Reset value0 EN A 1 in this bit shows that the STATUS interrupt has beenenabled and that the STATUS interrupt request signal isasserted when STAT = 1 in the STATUS register.031:1 - Reserved. -Table 769. Interrupt clear status register (CLR_STAT - 0x4004 0FE8) bit descriptionBit Symbol Description Reset value0 CSTAT Writing a 1 to this bit clears the STATUS interrupt bit in theSTATUS register.031:1 - Reserved. -Table 770. Interrupt set status register (SET_STAT - 0x4004 0FEC) bit descriptionBit Symbol Description Reset value0 SSTAT Writing a 1 to this bit sets the STATUS interrupt bit in theSTATUS register.031:1 - Reserved. -