NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 129 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 129 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.7.4.3.5 Mode 1d: Normal operating mode with post-divider and with pre-dividerIn normal operating mode 1d none of the dividers are bypassed. The operatingfrequencies are:Fout = Fcco /(2 x P) = M x Fin /(N x P)  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150MHz)The divider ratios are programmable:• Pre-divider N (N, 1 to 256)• Feedback-divider M (M, 1 to 2 15)• Post-divider P (P, 1 to 32)11.7.4.3.6 Mode 3: Power down mode (pd)In this mode (pd = '1'), the oscillator will be stopped, the lock output will be made low, andthe internal current reference will be turned off. During pd it is also possible to load newdivider ratios at the input buses (msel, psel, nsel). Power-down mode is ended by makingpd low, causing the PLL to start up. The lock signal will be made high once the PLL hasregained lock on the input clock.11.7.4.4 Settings for USB0Table 94 shows the divider settings used for configuring an output frequency F out of480 MHz for USB0.11.7.4.5 Usage notesIn order to set up the PLL0, follow these steps:1. Power down the PLL0 by setting bit 1 in the PLL0_CTRL register to 1. This step isonly needed if the PLL0 is currently enabled.2. Configure the PLL0 m, n, and p divider values in the PLL0_M and PLL0_NP registers.3. Power up the PLL0 by setting bit 1 in the PLL0_CTRL register to 0.4. Wait for the PLL0 to lock by monitoring the LOCK bit in the PLL0_STAT register.5. Enable the PLL0 clock output in the PLL0_CTRL register.Remark: You can change the PLL0 settings while the PLL0 is running when you need toconfigure the PLL0 for high output frequencies (see Section 11.2.1).11.7.5 Fractional divider for PLL0AUDIOThe PLL0 for audio applications (PLL0AUDIO) includes an additional fractional divider.The SEL_EXT bit in the PLL0AUDIO control register determines whether the fractionaldivider is used (SEL_EXT=0) or bypassed (SEL_EXT=1). In the latter case, PLL0AUDIOoperates exactly as PLL0USB and the MDEC value is used directly to control thefeedback divider.When the fractional divider is active, the sigma-delta modulator block generates dividervalues M and M+1 in the correct proportion so that an average division ratio of M+K/L isrealized where 0<=K<=L and M, K, and L are integer values. M Is determined by theinteger part of the PLLFRACT_CTRL register (PLLFRACT[21:15]) and K is determined by