NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 386 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 386 of 1269NXP Semiconductors UM10503Chapter 19: LPC43xx General Purpose DMA (GPDMA) controllerSREQ[15:0] — Single transfer request signals. These cause a single data to betransferred. The DMA controller transfers a single transfer to or from the peripheral.LBREQ[15:0] — Last burst request signals.LSREQ[15:0] — Last single transfer request signals.Note that most peripherals do not support all request types.19.5.2 DMA response signalsThe DMA response signals indicate whether the transfer initiated by the DMA requestsignal has completed. The response signals can also be used to indicate whether acomplete packet has been transferred. The DMA response signals from the DMAcontroller are:CLR[15:0] — DMA clear or acknowledge signals. The CLR signal is used by the DMAcontroller to acknowledge a DMA request from the peripheral.TC[15:0] — DMA terminal count signals. The TC signal can be used by the DMAcontroller to indicate to the peripheral that the DMA transfer is complete.19.6 Register descriptionThe DMA Controller supports 8 channels. Each channel has registers specific to theoperation of that channel. Other registers controls aspects of how source peripheralsrelate to the DMA Controller. There are also global DMA control and status registers.Table 271. Register overview: GPDMA (base address 0x4000 2000)Name Access AddressoffsetDescription Reset value ReferenceGeneral registersINTSTAT RO 0x000 DMA Interrupt Status Register 0x0000 0000 Table 272INTTCSTAT RO 0x004 DMA Interrupt Terminal Count Request StatusRegister0x0000 0000 Table 273INTTCCLEAR WO 0x008 DMA Interrupt Terminal Count Request ClearRegister- Table 274INTERRSTAT RO 0x00C DMA Interrupt Error Status Register 0x0000 0000 Table 275INTERRCLR WO 0x010 DMA Interrupt Error Clear Register - Table 276RAWINTTCSTAT RO 0x014 DMA Raw Interrupt Terminal Count StatusRegister0x0000 0000 Table 277RAWINTERRSTATRO 0x018 DMA Raw Error Interrupt Status Register 0x0000 0000 Table 278ENBLDCHNS RO 0x01C DMA Enabled Channel Register 0x0000 0000 Table 279SOFTBREQ R/W 0x020 DMA Software Burst Request Register 0x0000 0000 Table 280SOFTSREQ R/W 0x024 DMA Software Single Request Register 0x0000 0000 Table 281SOFTLBREQ R/W 0x028 DMA Software Last Burst Request Register 0x0000 0000 Table 282SOFTLSREQ R/W 0x02C DMA Software Last Single Request Register 0x0000 0000 Table 283CONFIG R/W 0x030 DMA Configuration Register 0x0000 0000 Table 284SYNC R/W 0x034 DMA Synchronization Register 0x0000 0000 Table 285Channel 0 registers