NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1256 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1256 of 1269NXP Semiconductors UM10503Chapter 50: Supplementary information21.7.6 Dynamic Memory Read Configurationregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47721.7.7 Dynamic Memory Precharge Command Periodregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47821.7.8 Dynamic Memory Active to Precharge CommandPeriod register . . . . . . . . . . . . . . . . . . . . . . . 47821.7.9 Dynamic Memory Self Refresh Exit Timeregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47921.7.10 Dynamic Memory Last Data Out to Active Timeregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47921.7.11 Dynamic Memory Data In to Active CommandTime register . . . . . . . . . . . . . . . . . . . . . . . . 47921.7.12 Dynamic Memory Write Recovery Timeregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48021.7.13 Dynamic Memory Active to Active CommandPeriod register . . . . . . . . . . . . . . . . . . . . . . . 48021.7.14 Dynamic Memory Auto-refresh Periodregister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48121.7.15 Dynamic Memory Exit Self Refresh register 48121.7.16 Dynamic Memory Active Bank A to Active Bank BTime register . . . . . . . . . . . . . . . . . . . . . . . . 48121.7.17 Dynamic Memory Load Mode register to ActiveCommand Time . . . . . . . . . . . . . . . . . . . . . . 48221.7.18 Static Memory Extended Wait register . . . . . 48221.7.19 Dynamic Memory Configuration registers . . 48321.7.20 Dynamic Memory RAS & CAS Delayregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48521.7.21 Static Memory Configuration registers . . . . . 48621.7.22 Static Memory Write Enable Delay registers 48821.7.23 Static Memory Output Enable Delayregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . 48821.7.24 Static Memory Read Delay registers . . . . . . 48921.7.25 Static Memory Page Mode Read Delay registers48921.7.26 Static Memory Write Delay registers . . . . . . 49021.7.27 Static Memory Turn Round Delay registers 49021.8 Functional description . . . . . . . . . . . . . . . . . 49221.8.1 AHB slave register interface . . . . . . . . . . . . 49221.8.2 AHB slave memory interface . . . . . . . . . . . . 49221.8.2.1 Memory transaction endianness . . . . . . . . . 49221.8.2.2 Memory transaction size . . . . . . . . . . . . . . . 49221.8.2.3 Write protected memory areas. . . . . . . . . . . 49221.8.3 Pad interface . . . . . . . . . . . . . . . . . . . . . . . . 49221.8.4 Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . 49321.8.4.1 Write buffers. . . . . . . . . . . . . . . . . . . . . . . . . 49321.8.4.2 Read buffers . . . . . . . . . . . . . . . . . . . . . . . . 49321.8.5 Using the EMC with SDRAM . . . . . . . . . . . . 49421.8.5.1 SDRAM burst length . . . . . . . . . . . . . . . . . . 49421.8.5.2 SDRAM mode register burst length set-up . 49421.8.5.2.1 Example for setting the SDRAM moderegister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49621.8.5.3 Self-refresh mode . . . . . . . . . . . . . . . . . . . . 49621.8.6 External static memory interface . . . . . . . . . 49721.8.6.1 32-bit wide memory bank connection . . . . . 49721.8.6.2 16-bit wide memory bank connection . . . . . 49821.8.6.3 8-bit wide memory bank connection . . . . . . 499Chapter 22: LPC43xx SPI Flash Interface (SPIFI)22.1 How to read this chapter . . . . . . . . . . . . . . . . 50022.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 50022.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50022.4 General description . . . . . . . . . . . . . . . . . . . 50022.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . 50122.6 Supported QSPI devices . . . . . . . . . . . . . . . 501Chapter 23: LPC43xx USB0 Host/Device/OTG controller23.1 How to read this chapter . . . . . . . . . . . . . . . . 50323.2 Basic configuration . . . . . . . . . . . . . . . . . . . . 50323.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50323.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 50423.4.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . 50423.4.2 About USB On-The-Go. . . . . . . . . . . . . . . . . 50423.4.3 USB acronyms and abbreviations . . . . . . . . 50523.4.4 Transmit and receive buffers . . . . . . . . . . . . 50523.4.5 Fixed endpoint configuration. . . . . . . . . . . . . 50523.5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 50623.5.1 Requirements for connecting theUSB0_VBUS/USB1_VBUS signal . . . . . . . . 50723.6 Register description . . . . . . . . . . . . . . . . . . . 50723.6.1 Use of registers . . . . . . . . . . . . . . . . . . . . . . 50923.6.2 Device/host capability registers . . . . . . . . . . 51023.6.3 USB Command register (USBCMD). . . . . . . 51223.6.3.1 Device mode. . . . . . . . . . . . . . . . . . . . . . . . . 51223.6.3.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51323.6.4 USB Status register (USBSTS). . . . . . . . . . . 51523.6.4.1 Device mode. . . . . . . . . . . . . . . . . . . . . . . . . 51623.6.4.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51823.6.5 USB Interrupt register (USBINTR) . . . . . . . . 52023.6.5.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . 52023.6.5.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52123.6.6 Frame index register (FRINDEX). . . . . . . . . 52223.6.6.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . 52223.6.6.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52223.6.7 Device address (DEVICEADDR - device) andPeriodic List Base (PERIODICLISTBASE- host)registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52323.6.7.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . 52323.6.7.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52323.6.8 Endpoint List Address register(ENDPOINTLISTADDR - device) andAsynchronous List Address (ASYNCLISTADDR -host) registers . . . . . . . . . . . . . . . . . . . . . . . 52423.6.8.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . 52423.6.8.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 52423.6.9 TT Control register (TTCTRL) . . . . . . . . . . . 52423.6.9.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . 52423.6.9.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . 525