UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 241 of 1269NXP Semiconductors UM10503Chapter 14: LPC43xx Pin configurationP3_3 B14 B13 169 [5] N;PU- R — Function reserved.I/O SPI_SCK — Serial clock for SPI.I/O SSP0_SCK — Serial clock for SSP0.O SPIFI_SCK — Serial clock for SPIFI.O CGU_OUT1 — CGU spare clock output 1.- R — Function reserved.O I2S0_TX_MCLK — I2S transmit master clock.I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master andreceived by the slave. Corresponds to the signal SCK in the I 2S-busspecification.P3_4 A15 C14 171 [3] N;PUI/O GPIO1[14] — General purpose digital input/output pin.- R — Function reserved.- R — Function reserved.I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.O U1_TXD — Transmitter output for UART 1.I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master andreceived by the slave. Corresponds to the signal WS in the I2 S-busspecification.I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the transmitterand read by the receiver. Corresponds to the signal SD in the I 2 S-busspecification.O LCD_VD13 — LCD data.P3_5 C12 C11 173 [3] N;PUI/O GPIO1[15] — General purpose digital input/output pin.- R — Function reserved.- R — Function reserved.I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.I U1_RXD — Receiver input for UART 1.I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitterand read by the receiver. Corresponds to the signal SD in the I 2 S-busspecification.I/O I2S1_RX_WS — Receive Word Select. It is driven by the master andreceived by the slave. Corresponds to the signal WS in the I2 S-busspecification.O LCD_VD12 — LCD data.Table 130. LPC4357/53 Pin description …continuedPin nameLBGA256TFBGA180LQFP208Reset state[2]TypeDescription