NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 803 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 803 of 1269NXP Semiconductors UM10503Chapter 27: LPC43xx LCD(1) Signal polarities may vary for some displays.Fig 84. Vertical timing for STN displaysLCD_TIMV (VSW)LCDDCLK(panel clock)LCD_TIMV (VBP) LCD_TIMV(LPP) LCD_TIMV (VFP)LCDFP(vertical synchpulse)back porch(defined in line clocks) front porch(defined in line clocks)pixel dataand horizontalcontrols for oneframeone frameall horizontal lines for one framesee horizontal timing for STN displayspanel data clock active(1) The active data lines will vary with the type of TFT panel.(2) The LCD panel clock is selected and scaled by the LCD controller and used to produce LCDCLK.(3) The duration of the LCDLP is controlled by the HSW field in the TIMH register.(4) The polarity of the LCDLP signal is determined by the IHS bit in the POL register.Fig 85. Horizontal timing for TFT displayspixel clock(internal)LCD_TIMH (HSW)LCDLP(lhorizontalsynch pulse)LCD_TIMH (HBP) LCD_TIMH(PPL) LCD_TIMH (HFP)LCDDCLK(panel clock)LCDENABhorizontal back porch(defined in pixel clocks) horizontal front porch(defined in pixel clocks)one horizontal line of LCD dataLCDVD[23:0](panel data)one horizontal line