NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 861 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 861 of 1269NXP Semiconductors UM10503Chapter 29: LPC43xx Timer0/1/2/3Effective processing of the externally supplied clock to the counter has some limitations.Since two successive rising edges of the PCLK clock are used to identify only one edgeon the CAP selected input, the frequency of the CAP input can not exceed one quarter ofthe PCLK clock. Consequently, duration of the high/low levels on the same CAP input inthis case can not be shorter than 1/(2 PCLK).29.7 Functional description29.7.1 Example timer operationFigure 96 shows a timer configured to reset the count and generate an interrupt on match.The prescaler is set to 2 and the match register set to 6. At the end of the timer cyclewhere the match occurs, the timer count is reset. This gives a full length cycle to thematch value. The interrupt indicating that a match occurred is generated in the next clockafter the timer reached the match value.Table 695. Timer count control register (CTCR - addresses 0x4008 4070 (TIMER0),0x4008 5070 (TIMER1), 0x400C 3070 (TIMER2), 0x400C 4070 (TIMER3)) bitdescriptionBit Symbol Value Description Resetvalue1:0 CTMODE Counter/Timer ModeThis field selects which rising PCLK edges can incrementTimer’s Prescale Counter (PC), or clear PC and incrementTimer Counter (TC).Timer Mode: the TC is incremented when the PrescaleCounter matches the Prescale Register.000x0 Timer Mode: every rising PCLK edge0x1 Counter Mode: TC is incremented on rising edges on theCAP input selected by bits 3:2.0x2 Counter Mode: TC is incremented on falling edges on theCAP input selected by bits 3:2.0x3 Counter Mode: TC is incremented on both edges on theCAP input selected by bits 3:2.3:2 CINSEL Count Input SelectWhen bits 1:0 in this register are not 00, these bits selectwhich CAP pin is sampled for clocking.Note: If Counter mode is selected for a particular CAPninput in the TnCTCR, the 3 bits for that input in the CaptureControl Register (TnCCR) must be programmed as 000.However, capture and/or interrupt can be selected for theother 3 CAPn inputs in the same timer.000x0 CAPn.0 for TIMERn0x1 CAPn.1 for TIMERn0x2 CAPn.2 for TIMERn0x3 CAPn.3 for TIMERn31:4 - - Reserved, user software should not write ones to reservedbits. The value read from a reserved bit is not defined.NA