NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 621 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 621 of 1269NXP Semiconductors UM10503Chapter 24: LPC43xx USB1 Host/Device controller24.6.17 USB Endpoint Setup Status register (ENDPSETUPSTAT)24.6.18 USB Endpoint Prime register (ENDPTPRIME)For each endpoint, software should write a one to the corresponding bit whenever postinga new transfer descriptor to an endpoint. Hardware will automatically use this bit to beginparsing for a new transfer descriptor from the queue head and prepare a receive buffer.Hardware will clear this bit when the associated endpoint(s) is (are) successfully primed.Remark: These bits will be momentarily set by hardware during hardware endpointre-priming operations when a dTD is retired and the dQH is updated.4 SDIS Stream disable modeRemark: The use of this feature substantially limits the overall USBperformance that can be achieved.0 R/W0 Not disabled1 Disabled.Setting to a 1 ensures that overruns/underruns of the latency FIFO areeliminated for low bandwidth systems where the RX and TX buffers aresufficient to contain the entire packet. Enabling stream disable also has theeffect of ensuring the TX latency is filled to capacity before the packet islaunched onto the USB.Note: Time duration to pre-fill the FIFO becomes significant when streamdisable is active. See TXFILLTUNING to characterize the adjustmentsneeded for the scheduler when using this feature.5 VBPS VBUS power select 0 R/WO0 vbus_pwr_select is set LOW.1 vbus_pwr_select is set HIGH31:6 - - Reserved - -Table 485. USB Mode register in host mode (USBMODE_H - address 0x4000 71A8) bit description …continuedBit Symbol Value Description ResetvalueAccessTable 486. USB Endpoint Setup Status register (ENDPTSETUPSTAT - address 0x4000 71AC) bit descriptionBit Symbol Description ResetvalueAccess3:0 ENDPTSETUPSTATSetup endpoint status for logical endpoints.For every setup transaction that is received, a corresponding bit in this registeris set to one. Software must clear or acknowledge the setup transfer by writinga one to a respective bit after it has read the setup data from Queue head. Theresponse to a setup packet as in the order of operations and total responsetime is crucial to limit bus time outs while the setup lockout mechanism isengaged.0 R/WC31:4 - Reserved - -