NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 107 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 107 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.6.3.3 PLL0USB M-divider registerRemark: The PLL M-divider register does not use the direct binary representations of Mdirectly. Instead, it uses an encoded version MDEC of M. The valid range for M is 1 to2^15. This value is encoded into a 17-bit MDEC value.The relationship between M and MDEC is expressed via the following pseudo-code. Forspecific examples see Section 11.8.3 and Section 11.8.4.M_max=0x00008000, x=0x00004000;switch (M) {case 0: x = 0xFFFFFFFF;3 DIRECTO PLL0 direct output 0 R/W4 CLKEN PLL0 clock enable 0 R/W5 - Reserved - -6 FRM Free running mode 0 R/W7 - Reserved 0 R/W8 - Reserved. Reads as zero. Do not writeone to this register.0 R/W9 - Reserved. Reads as zero. Do not writeone to this register.0 R/W10 - Reserved. Reads as zero. Do not writeone to this register.0 R/W11 AUTOBLOCK Block clock automatically during frequencychange0 R/W0 Autoblocking disabled1 Autoblocking enabled23:12 - Reserved - -28:24 CLK_SEL Clock source selection. All other valuesare reserved.0x01 R/W0x00 32 kHz oscillator0x01 IRC (default)0x02 ENET_RX_CLK0x03 ENET_TX_CLK0x04 GP_CLKIN0x06 Crystal oscillator0x09 PLL10x0C IDIVA0x0D IDIVB0x0E IDIVC0x0F IDIVD0x10 IDIVE31:29 - Reserved - -Table 71. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit description…continuedBit Symbol Value Description ResetvalueAccess