NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 296 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 296 of 1269NXP Semiconductors UM10503Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration15.4.6 ADC0 function select registerFor pins with digital and analog functions, this register selects the input channel of theADC0 over any of the possible digital functions. This option is not available for channelADC0_7.In addition, each analog function is pinned out on a dedicated analog pin which is notaffected by this register.The following pins are controlled by the ENAIO0 register:3 SCL_EZI Enable the input receiver for the SCL pin.Always write a 1 to this bit when using theI2C0.0 R/W0 Disabled1 Enabled6:4 - Reserved - -7 SCL_ZIF Enable or disable input glitch filter for theSCL pin. The filter time constant isdetermined by bit EFP.0 R/W0 Enable input filter1 Disable input filter8 SDA_EFP Select input glitch filter time constant for theSDA pin.0 R/W0 50 ns glitch filter1 3 ns glitch filter9 - Reserved. Always write a 0 to this bit. 0 R/W10 SDA_EHD Select I2C mode for the SDA pin. 0 R/W0 Standard/Fast mode transmit1 Fast-mode Plus transmit11 SDA_EZI Enable the input receiver for the SDA pin.Always write a 1 to this bit when using theI2C0.0 R/W0 Disabled1 Enabled14:12 - Reserved - -15 SDA_ZIF Enable or disable input glitch filter for theSDA pin. The filter time constant isdetermined by bit SDA_EFP.0 R/W0 Enable input filter1 Disable input filter31:16 - Reserved - -Table 137. Pin configuration for open-drain I 2C-bus pins register (SFSI2C0, address 0x40086C84) bit description …continuedBit Symbol Value Description ResetvalueAccess