NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 479 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 479 of 1269NXP Semiconductors UM10503Chapter 21: LPC43xx External Memory Controller (EMC)21.7.9 Dynamic Memory Self Refresh Exit Time registerThe DYNAMICTSREX register enables you to program the self-refresh exit time, tSREX.It is recommended that this register is modified during system initialization, or when thereare no current or outstanding transactions. This can be ensured by waiting until the EMCis idle, and then entering low-power, or disabled mode. This value is normally found inSDRAM data sheets as tSREX, for devices without this parameter you use the samevalue as tXSR. This register is accessed with one wait state.Note: This register is used for all four dynamic memory chip selects. Therefore the worstcase value for all of the chip selects must be programmed.21.7.10 Dynamic Memory Last Data Out to Active Time registerThe DYNAMICTAPR register enables you to program the last-data-out to active commandtime, tAPR. It is recommended that this register is modified during system initialization, orwhen there are no current or outstanding transactions. This can be ensured by waitinguntil the EMC is idle, and then entering low-power, or disabled mode. This value isnormally found in SDRAM data sheets as tAPR. This register is accessed with one waitstate.Note: This register is used for all four dynamic memory chip selects. Therefore the worstcase value for all of the chip selects must be programmed.21.7.11 Dynamic Memory Data In to Active Command Time registerThe DYNAMICTDAL register enables you to program the data-in to active command time,tDAL. It is recommended that this register is modified during system initialization, or whenthere are no current or outstanding transactions. This can be ensured by waiting until theEMC is idle, and then entering low-power, or disabled mode. This value is normally foundin SDRAM data sheets as tDAL, or tAPW. This register is accessed with one wait state.Note: This register is used for all four dynamic memory chip selects. Therefore the worstcase value for all of the chip selects must be programmed.Table 362. Dynamic Memory Self Refresh Exit Time register (DYNAMICSREX - address0x4000 5038) bit descriptionBit Symbol Description Resetvalue3:0 TSREX Self-refresh exit time.0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.0xF = 16 clock cycles (POR reset value).0xF31:4 - Reserved, user software should not write ones to reserved bits. Thevalue read from a reserved bit is not defined.-Table 363. Dynamic Memory Last Data Out to Active Time register (DYNAMICAPR - address0x4000 503C) bit descriptionBit Symbol Description Resetvalue3:0 TAPR Last-data-out to active command time.0x0 - 0xE = n + 1 clock cycles. The delay is in CCLK cycles.0xF = 16 clock cycles (POR reset value).0xF31:4 - Reserved, user software should not write ones to reserved bits. Thevalue read from a reserved bit is not defined.-