NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 911 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 911 of 126932.1 How to read this chapterThe RIT is available on all LPC43xx parts.32.2 Basic configurationThe RIT is configured as follows:• See Table 755 for clocking and power control.• The RIT is reset by the RITIMER_RST (reset #36).• The RIT interrupt is connected to slot # 11 in the NVIC.32.3 Features• 32-bit counter running from BASE_M4_CLK. Counter can be free-running, or be resetby a generated interrupt.• 32-bit compare value.• 32-bit compare mask. An interrupt is generated when the counter value equals thecompare value after masking. This allows for combinations not possible with a simplecompare.32.4 General descriptionThe Repetitive Interrupt Timer (RIT) provides a versatile means of generating interrupts atspecified time intervals, without using a standard timer. It is intended for repeatinginterrupts that aren’t related to Operating System interrupts. The RIT could also be usedas an alternative to the Cortex-M4 System Tick Timer if there are different systemrequirements.UM10503Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT)Rev. 1.3 — 6 July 2012 User manualTable 755. RIT clocking and power controlBase clock Branch clock OperatingfrequencyClock to the RI timer register interface andRI timer peripheral clock (PCLK).BASE_M4_CLK CLK_M4_RITIMER up to204 MHz