NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 375 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 375 of 1269NXP Semiconductors UM10503Chapter 18: LPC43xx Serial GPIO (SGPIO)18.8.1 Multi-channel I2S18.8.1.1 I2S slice selectionA 5.1 channel I2S output interface in master mode requires 3 data outputs (SD[2:0]), 1word select output (WS) and 1 clock output (SCK). In slave mode SCK becomes an input.This means that output SCK should also support clock input. This is supported by pins8-10 which are mapped in serial output mode to slices B, M, G or N, let's use slice B.These slices should therefore not be used for SD or WS signals.If an oversampled slave clock (MCK) is needed, use a slice that is capable to createclocks for other slices (D, H, O or P), e.g. use slice D. In slave mode MCK is an input.MCK is divided down to create the shift clock for Data, WS and SCK. In master modeMCK is an output.The output audio data rate is 6 x Fs. For Fs = 192 kHz this becomes 1.152 MWps andthus relative low for a CPU frequency of 100+ MHz. Single slices can be used (withoutconcatenation), for example slices A, I and E. The WS is made by slice J. This results inthe following mapping:Table 258. SGPIO Slice mapping for I2S 5.1Slice: function A,I,E : SD[2:0] J : WS B : SCK D : MCKFig 40. 5.1 channel I2S output mapped to SGPIO slicesslice Aslice Isckinsd0slice Eslice Jsckmcksd2sd1wsslice Bcounter Dmckinpin 0pin 1pin 2pin 3pin 8pin 12counter Acounter Icounter Ecounter Jslave to sckslave to mckcounter Bsgpio _clkslice DMCK/4