NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 144 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 144 of 1269NXP Semiconductors UM10503Chapter 12: LPC43xx Clock Control Unit (CCU)CLK_M4_WWDT_CFG R/W 0x500 CLK_M4_WWDT configuration register 0x0000 0001 Table 105CLK_M4_WWDT_STAT R 0x504 CLK_M4_WWDT status register 0x0000 0001 Table 108CLK_M4_USART0_CFG R/W 0x508 CLK_M4_UART0 configuration register 0x0000 0001 Table 105CLK_M4_USART0_STAT R 0x50C CLK_M4_UART0 status register 0x0000 0001 Table 108CLK_M4_UART1_CFG R/W 0x510 CLK_M4_UART1 configuration register 0x0000 0001 Table 105CLK_M4_UART1_STAT R 0x514 CLK_M4_UART1 status register 0x0000 0001 Table 108CLK_M4_SSP0_CFG R/W 0x518 CLK_M4_SSP0 configuration register 0x0000 0001 Table 105CLK_M4_SSP0_STAT R 0x51C CLK_M4_SSP0 status register 0x0000 0001 Table 108CLK_M4_TIMER0_CFG R/W 0x520 CLK_M4_TIMER0 configuration register 0x0000 0001 Table 105CLK_M4_TIMER0_STAT R 0x524 CLK_M4_TIMER0 status register 0x0000 0001 Table 108CLK_M4_TIMER1_CFG R/W 0x528 CLK_M4_TIMER1 configuration register 0x0000 0001 Table 105CLK_M4_TIMER1_STAT R 0x52C CLK_M4_TIMER1 status register 0x0000 0001 Table 108CLK_M4_SCU_CFG R/W 0x530 CLK_M4_SCU configuration register 0x0000 0001 Table 105CLK_M4_SCU_STAT R 0x534 CLK_M4_SCU status register 0x0000 0001 Table 108CLK_M4_CREG_CFG R/W 0x538 CLK_M4_CREG configuration register 0x0000 0001 Table 105CLK_M4_CREG_STAT R 0x53C CLK_M4_CREG status register 0x0000 0001 Table 108- - 0x540 to0x5FCReserved - -CLK_M4_RITIMER_CFG R/W 0x600 CLK_M4_RITIMER configuration register 0x0000 0001 Table 105CLK_M4_RITIMER_STAT R 0x604 CLK_M4_RITIMER status register 0x0000 0001 Table 108CLK_M4_USART2_CFG R/W 0x608 CLK_M4_UART2 configuration register 0x0000 0001 Table 105CLK_M4_USART2_STAT R 0x60C CLK_M4_UART2 status register 0x0000 0001 Table 108CLK_M4_USART3_CFG R/W 0x610 CLK_M4_UART3 configuration register 0x0000 0001 Table 105CLK_M4_USART3_STAT R 0x614 CLK_M4_UART3 status register 0x0000 0001 Table 108CLK_M4_TIMER2_CFG R/W 0x618 CLK_M4_TIMER2 configuration register 0x0000 0001 Table 105CLK_M4_TIMER2_STAT R 0x61C CLK_M4_TIMER2 status register 0x0000 0001 Table 108CLK_M4_TIMER3_CFG R/W 0x620 CLK_M4_TIMER3 configuration register 0x0000 0001 Table 105CLK_M4_TIMER3_STAT R 0x624 CLK_M4_TIMER3 status register 0x0000 0001 Table 108CLK_M4_SSP1_CFG R/W 0x628 CLK_M4_SSP1 configuration register 0x0000 0001 Table 105CLK_M4_SSP1_STAT R 0x62C CLK_M4_SSP1 status register 0x0000 0001 Table 108CLK_M4_QEI_CFG R/W 0x630 CLK_M4_QEI configuration register 0x0000 0001 Table 105CLK_M4_QEI_STAT R 0x634 CLK_M4_QEI status register 0x0000 0001 Table 108- R/W 0x638 to0x6FCReserved - -CLK_PERIPH_BUS_CFG R/W 0x700 CLK_PERIPH_BUS configuration register 0x0000 0001 Table 105CLK_PERIPH_BUS_STAT R 0x704 CLK_PERIPH_BUS status register 0x0000 0001 Table 108- R/W 0x708 to0x70CReserved - -CLK_PERIPH_CORE_CFG R/W 0x710 CLK_PERIPH_CORE configurationregister0x0000 0001 Table 105CLK_PERIPH_CORE_STAT R 0x714 CLK_PERIPH_CORE status register 0x0000 0001 Table 108Table 100. Register overview: CCU1 (base address 0x4005 1000)Name Access AddressoffsetDescription Reset value Reference