UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 693 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx EthernetRemark: Reset values in this register are valid only if the clocks to the Ethernet block arepresent during the reset operation.Table 541. MAC Debug register (MAC_DEBUG, address 0x4001 0024) bit descriptionBit Symbol Description ResetvalueAccess0 RXIDLESTAT When high, it indicates that the MAC MII receive protocol engine is activelyreceiving data and not in IDLE state.0 RO2:1 FIFOSTAT0 When high, it indicates the active state of the small FIFO Read and Writecontrollers respectively of the MAC receive Frame Controller module.0 RO3 - Reserved - RO4 RXFIFOSTAT1 When high, it indicates that the MTL RxFIFO Write Controller is active andtransferring a received frame to the FIFO.0 RO6:5 RXFIFOSTAT State of the RxFIFO read Controller:00 = idle state01 = reading frame data10 = reading frame status (or time stamp)11 = flushing the frame data and status0 RO7 - Reserved - RO9:8 RXFIFOLVL Status of the RxFIFO Fill-level00 = RxFIFO Empty01 = RxFIFO fill-level below flow-control de-activate threshold10 = RxFIFO fill-level above flow-control activate threshold11 = RxFIFO Full0 RO15:10 - Reserved - RO16 TXIDLESTAT When high, it indicates that the MAC MII transmit protocol engine is activelytransmitting data and not in IDLE state.0 RO18:17 TXSTAT State of the MAC Transmit Frame Controller module:00 = idle01 = Waiting for Status of previous frame or IFG/backoff period to be over10 = Generating and transmitting a PAUSE control frame (in full duplex mode)11 = Transferring input frame for transmission0 RO19 PAUSE When high, it indicates that the MAC transmitter is in PAUSE condition (infull-duplex only) and hence will not schedule any frame for transmission.0 RO21:20 TXFIFOSTAT State of the TxFIFO read Controller00 = idle state01 = READ state (transferring data to MAC transmitter)10 = Waiting for TxStatus from MAC transmitter11 = Writing the received TxStatus or flushing the TxFIFO0 RO22 TXFIFOSTAT1 When high, it indicates that the TxFIFO Write Controller is active andtransferring data to the TxFIFO.0 RO23 - Reserved 0 RO24 TXFIFOLVL When high, it indicates that the TxFIFO is not empty and has some data left fortransmission.0 RO25 TXFIFOFULL When high, it indicates that the TxStatus FIFO is full and hence the controllerwill not be accepting any more frames for transmission.0 RO31:26 - Reserved - RO