NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 382 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 382 of 126919.1 How to read this chapterThe GPDMA is available on all LPC43xx parts.Remark: The VADC is not available on parts LPC4350/30/20/10.19.2 Basic configurationThe GPDMA is configured as follows:• See Table 269 for clocking and power control.• The GPDMA is reset by the DMA_RST (reset # 19).• The DMAMUX register in the CREG block (see Table 46) selects between up to threeperipherals for each GPDMA-to-peripheral line.• The GPIO block, the WWDT, and the timers can be accessed by the GPDMA asmemory-to-memory transfers.19.3 Features• Eight DMA channels. Each channel can support an unidirectional transfer.• 16 DMA request lines.• Single DMA and burst DMA request signals. Each peripheral connected to the DMAController can assert either a burst DMA request or a single DMA request. The DMAburst size is set by programming the DMA Controller.• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, andperipheral-to-peripheral transfers are supported.• The GPIO block, the WWDT, and the timers can be accessed by the GPDMA asmemory-to-memory transfers.• Scatter or gather DMA is supported through the use of linked lists. This means thatthe source and destination areas do not have to occupy contiguous areas of memory.• Hardware DMA channel priority.• AHB slave DMA programming interface. The DMA Controller is programmed bywriting to the DMA control registers over the AHB slave interface.• Two AHB bus masters for transferring data. These interfaces transfer data when aDMA request goes active. Master 1 can access memories and peripherals, master 0can access memories only.• 32-bit AHB master bus width.UM10503Chapter 19: LPC43xx General Purpose DMA (GPDMA)controllerRev. 1.3 — 6 July 2012 User manualTable 269. GPDMA clocking and power controlBase clock Branch clock Operating frequencyGPDMA BASE_M4_CLK CLK_M4_DMA 204 MHz