NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 548 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 548 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controllerconsumption rate, then software can reduce the SOF length using the USB0FLADJregister. The USB bit clock is still running at the normal rate so no bus errors occur. Thehost only changes when it introduces the next SOF token - earlier or later on a bit-timeresolution boundary. Adding the SOF token early allows to obtain more data over thecourse of the transmission.The registers to control the frame length are located in the CREG block (see Table 55).23.7.8 Hardware assistThe hardware assist provides automated response and sequencing that may not bepossible in software if there are significant interrupt latency response times. The use ofthis additional circuitry is optional and can be used to assist the following three statetransitions by setting the appropriate bits in the OTGSC register:• Auto reset (set bit HAAR).• Data pulse (set bit HADP).• B-disconnect to A-connect (set bit HABA).23.7.8.1 Auto resetWhen the HAAR in the OTGSC register is set to one, the host will automatically start areset after a connect event. This shortcuts the normal process where software is notifiedof the connect event and starts the reset. Software will still receive notification of theconnect event (CCS bit in the PORTSC register) but should not write the reset bit in theUSBCMD register when the HAAR is set. Software will be notified again after the reset iscomplete via the enable change bit in the PORTSC register which causes a port changeinterrupt.This assist will ensure the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met (seeOTG specification for an explanation of the OTG timing requirements).23.7.8.2 Data pulseWriting a one to HADP in the OTGSC register will start a data pulse of approximately 7 msin duration and then automatically cease the data pulsing. During the data pulse, the DPbit will be set and then cleared. This automation relieves software from accuratelycontrolling the data-pulse duration. During the data pulse, the HCD can poll to see that theHADP and DP bit have returned low to recognize the completion, or the HCD can simplylaunch the data pulse and wait to see if a VBUS Valid interrupt occurs when the A-sidesupplies bus power.This assist will ensure data pulsing meets the OTG requirement of > 5 ms and < 10 ms.23.7.8.3 B-disconnect to A-connect (Transition to the A-peripheral state)During HNP, the B-disconnect occurs from the OTG A_suspend state, and within 3 ms,the A-device must enable the pull-up on the DP leg in the A-peripheral state. For thehardware assist to begin the following conditions must be met:• HABA is set.• Host controller is in suspend mode.• Device is disconnecting.