UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 196 of 1269NXP Semiconductors UM10503Chapter 14: LPC43xx Pin configurationP6_0 M12 M10 H7 105 73 [3] N;PU- R — Function reserved.O I2S0_RX_MCLK — I2S receive master clock.- R — Function reserved.- R — Function reserved.I/O I2S0_RX_SCK — Receive Clock. It is driven by themaster and received by the slave. Corresponds to thesignal SCK in the I2 S-bus specification.- R — Function reserved.- R — Function reserved.- R — Function reserved.P6_1 R15 P14 G5 107 74 [3] N;PUI/O GPIO3[0] — General purpose digital input/output pin.O EMC_DYCS1 — SDRAM chip select 1.I/O U0_UCLK — Serial clock input/output for USART0 insynchronous mode.I/O I2S0_RX_WS — Receive Word Select. It is driven by themaster and received by the slave. Corresponds to thesignal WS in the I 2S-bus specification.- R — Function reserved.I T2_CAP0 — Capture input 2 of timer 2.- R — Function reserved.- R — Function reserved.P6_2 L13 K11 J9 111 78 [3] N;PUI/O GPIO3[1] — General purpose digital input/output pin.O EMC_CKEOUT1 — SDRAM clock enable 1.I/O U0_DIR — RS-485/EIA-485 output enable/directioncontrol for USART0.I/O I2S0_RX_SDA — I2S Receive data. It is driven by thetransmitter and read by the receiver. Corresponds to thesignal SD in the I2 S-bus specification.- R — Function reserved.I T2_CAP1 — Capture input 1 of timer 2.- R — Function reserved.- R — Function reserved.Table 129. Pin description …continuedLCD, Ethernet, USB0, and USB1 functions are not available on all parts.SymbolLBGA256TFBGA180TFBGA100LQFP208[1]LQFP144Reset state[2]TypeDescription