NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 800 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 800 of 1269NXP Semiconductors UM10503Chapter 27: LPC43xx LCD1. When power is applied, the following signals are held LOW:• LCDLP• LCDDCLK• LCDFP• LCDENAB/ LCDM• LCDVD[23:0]• LCDLE2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. Thisenables the following signals into their active states:• LCDLP• LCDDCLK• LCDFP• LCDENAB/ LCDM• LCDLEThe LCDV[23:0] signals remain in an inactive state.3. When the signals in step 2 have stabilized, the contrast voltage (not controlled orsupplied by the LCD controller) is applied to the LCD panel.4. If required, a software or hardware timer can be used to provide the minimum displayspecific delay time between application of the control signals and power to the paneldisplay. On completion of the time interval, power is applied to the panel by writing a 1 tothe LcdPwr bit within the CTRL register that, in turn, sets the LCDPWR signal high andenables the LCDV[23:0] signals into their active states. The LCDPWR signal is intendedto be used to gate the power to the LCD panel.The power-down sequence is the reverse of the above four steps and must be strictlyfollowed, this time, writing the respective register bits with 0.Figure 82 shows the power-up and power-down sequences.