NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1058 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1058 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interface41.7.2.2.7 Receiver master mode (External MCLK)41.7.3 FIFO controllerHandling of data for transmission and reception is performed via the FIFO controller whichcan generate two DMA requests and an interrupt request. The controller consists of a setof comparators which compare FIFO levels with depth settings contained in registers. Thecurrent status of the level comparators can be seen in the APB status register.Table 925. Receiver master mode (External MCLK)CREG bit 13 DAI bit 5 RXMODEbits [3:0]Description0 0 0 0 0 1 Receiver master mode.The I2S receive function operates as a master.The receive clock source (RX_MCLK) is provided by the external master on theRX_MCLK pin.The WS used is the internally generated RX_WS.The RX_MCLK pin is enabled for input.Bold lines indicate the clock path for this configuration. CREG6 bits 12 and 13 select PLL0AUDIO for the I2S0 interface. CREGbits 14 and 15 select PLL0AUDIO for the I2S1 interface.Fig 148. Receiver master mode (External MCLK)I 2 Speripheralblock10I2SRXMODE[2]=0TX_SCKRX_SCK(1 to 64)TX_MCLKRX_MCLK8-bitFractionalRate DividerX YI2SDAI[5]=0I2STX_RATE[15:8]I2STX_RATE[7:0]0110I2SRXMODE[1:0]=00I2SRXBITRATE[5:0]10TX_WSRX_WSI2S_RX_WSI2SDAI[5]=0 Pin OEnI2S_RX_SDAI2S_RX_MCLKI2SRXMODE[3]=0I2S_RX_SCKPin OE010001CREG6[13]=001PLLAUDIOPCLKI2SRXMODE[2]=0