NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 509 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 509 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller23.6.1 Use of registersThe register interface has bit functions described for device mode and bit functionsdescribed for host mode. However, during OTG operations it is necessary to performtasks independent of the controller mode.The only way to transition the controller mode out of host or device mode is by setting thecontroller reset bit. Therefore, it is also necessary for the OTG tasks to be performedindependently of a controller reset as well as independently of the controller mode.- - 0x188 -0x1A0- - -OTGSC R/W 0x1A4 OTG status and control 0 0x00200D09Table 422USBMODE_D R/W 0x1A8 USB device mode (device mode) 0 0xA Table 423USBMODE_H R/W 0x1A8 USB device mode (host mode) 0 - Table 424Device endpoint registersENDPTSETUPSTAT R/W 0x1AC Endpoint setup status 0 0 Table 425ENDPTPRIME R/W 0x1B0 Endpoint initialization 0 0 Table 426ENDPTFLUSH R/W 0x1B4 Endpoint de-initialization 0 0 Table 427ENDPTSTAT RO 0x1B8 Endpoint status 0 0 Table 428ENDPTCOMPLETE R/W 0x1BC Endpoint complete 0 0 Table 429ENDPTCTRL0 R/W 0x1C0 Endpoint control 0 0 0 Table 430ENDPTCTRL1 R/W 0x1C4 Endpoint control 1 0 0 Table 431ENDPTCTRL2 R/W 0x1C8 Endpoint control 2 0 0 Table 431ENDPTCTRL3 R/W 0x1CC Endpoint control 3 0 0 Table 431ENDPTCTRL4 R/W 0x1D0 Endpoint control 4 0 0 Table 431ENDPTCTRL5 R/W 0x1D4 Endpoint control 5 0 0 Table 431Table 393. Register overview: USB0 OTG controller (register base address 0x4000 6000) …continuedName Access AddressoffsetDescription ResetvalueReset valueafter USB0bootReferenceFig 54. USB controller modesIDLEMODE = 00DEVICEMODE = 10HOSTMODE = 11Hardware reset orUSBCMD RST bit = 1write 10 to USBMODE write 11 to USBMODE