NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 159 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 159 of 1269NXP Semiconductors UM10503Chapter 13: LPC43xx Reset Generation Unit (RGU)13.4.1 RGU reset control registerThe RGU reset control register allows software to activate and clear individual resetoutputs. Each bit corresponds to an individual reset output, and writing a one activatesthat output. The reset output is automatically de-activated after a fixed delay period withthe exception of the M0APP_RST. If the reset output has a manual release, it staysactivated once pulled low until a 0 is written to the appropriate bit in this register. Thisapplies whether the reset activation came from the Reset Control Register or any othersourceRESET_EXT_STAT58 R/W 0x4E8 Reset external status register 58 forSPI_RST0x0 see Table 127RESET_EXT_STAT59 - 0x4EC Reserved - -RESET_EXT_STAT60 - 0x4F0 Reserved - -RESET_EXT_STAT61 - 0x4F4 Reserved - -RESET_EXT_STAT62 - 0x4F8 Reserved - -RESET_EXT_STAT63 - 0x4FC Reserved - -Table 113. Register overview: RGU (base address: 0x4005 3000) …continuedName Access AddressoffsetDescription Reset value ReferenceTable 114. Reset control register 0 (RESET_CTRL0, address 0x4005 3100) bit descriptionBit Symbol Description ResetvalueAccess0 CORE_RST Writing a one activates the reset. This bit is automatically cleared to 0after one clock cycle.0 W1 PERIPH_RST Writing a one activates the reset. This bit is automatically cleared to 0after three clock cycles.0 W2 MASTER_RST Writing a one activates the reset. This bit is automatically cleared to 0after three clock cycles.0 W3 - Reserved 0 -4 WWDT_RST Writing a one to this bit has no effect. 0 -5 CREG_RST Writing a one to this bit has no effect. 0 -6 - Reserved 0 -7 - Reserved 0 -8 BUS_RST Writing a one activates the reset. This bit is automatically cleared to 0after one clock cycle. Do not use during normal operation0 W9 SCU_RST Writing a one activates the reset. This bit is automatically cleared to 0after one clock cycle.0 W10 - Reserved 0 -11 - Reserved 0 -12 - Reserved 0 -13 M4_RST Writing a one activates the reset. This bit is automatically cleared to 0after one clock cycle.0 W14 - Reserved 0 -15 - Reserved 0 -16 LCD_RST Writing a one activates the reset. This bit is automatically cleared to 0after one clock cycle.0 W