NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1119 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1119 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interfaceSubsequent to an address-match detection, interrupts will be generated after each databyte is received for a slave-write transfer, or after each byte that the module “thinks” it hastransmitted for a slave-read transfer. In this second case, the data register will actuallycontain data transmitted by some other slave on the bus which was actually addressed bythe master.Following all of these interrupts, the processor may read the data register to see what wasactually transmitted on the bus.43.7.7.2 Loss of arbitration in Monitor modeIn monitor mode, the I2 C module will not be able to respond to a request for information bythe bus master or issue an ACK). Some other slave on the bus will respond instead. Thiswill most probably result in a lost-arbitration state as far as our module is concerned.Software should be aware of the fact that the module is in monitor mode and should notrespond to any loss of arbitration state that is detected.43.7.8 I2C Slave Address registersThese registers are readable and writable and are only used when an I 2 C interface is setto slave mode. In master mode, this register has no effect. The LSB of ADR is the GeneralCall bit. When this bit is set, the General Call address (0x00) is recognized.If these registers contain 0x00, the I 2 C will not acknowledge any address on the bus. Allfour registers (including ADR0, see Table 985) will be cleared to this disabled state onreset.43.7.9 I2C Data buffer registerIn monitor mode, the I2C module may lose the ability to stretch the clock (stall the bus) ifthe ENA_SCL bit is not set. This means that the processor will have a limited amount oftime to read the contents of the data received on the bus. If the processor reads the DATshift register, as it ordinarily would, it could have only one bit-time to respond to theinterrupt before the received data is overwritten by new data.To give the processor more time to respond, a new 8-bit, read-only DATA_BUFFERregister will be added. The contents of the 8 MSBs of the DAT shift register will betransferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plusACK or NACK) has been received on the bus. This means that the processor will havenine bit transmission times to respond to the interrupt and read the data before it isoverwritten.The processor will still have the ability to read DAT directly, as usual, and the behavior ofDAT will not be altered in any way.Table 991. I2 C Slave Address registers (ADR - address 0x400A 1020 (ADR1) to 0x400A 1028(ADR3) (I2C0) and 0x400E 0020 (ADR1) to 0x400E 0028 (ADR3) (I2C1)) bitdescriptionBit Symbol Description Reset value0 GC General Call enable bit. 07:1 Address The I2 C device address for slave mode. 0x0031:8 - Reserved. The value read from a reserved bit is not defined. -