NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 106 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 106 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)11.6.3 PLL0USB registersThe PLL0USB provides a dedicated clock to the High-speed USB0 interface.See Section 11.7.4.5 for instructions on how to set up the PLL0USB.11.6.3.1 PLL0USB status register11.6.3.2 PLL0USB control register1 BYPASS Configure crystal operation or external-clock inputpin XTAL1. Do not change the BYPASS andENABLE bits in one write-action: this will result inunstable device operation!0 R/W0 Operation with crystal connected (default).1 Bypass mode. Use this mode when an externalclock source is used instead of a crystal.2 HF Select frequency range 1 R/W0 Oscillator low-frequency mode (crystal or externalclock source 1 to 20 MHz). Between 15 MHz and20 MHz, the state of the HF bit is don’t care.1 Oscillator high-frequency mode; crystal or externalclock source 15 to 25 MHz. Between 15 MHz and20 MHz, the state of the HF bit is don’t care.31:3 - Reserved - -Table 69. XTAL_OSC_CTRL register (XTAL_OSC_CTRL, address 0x4005 0018) bitdescriptionBit Symbol Value Description ResetvalueAccessTable 70. PLL0USB status register (PLL0USB_STAT, address 0x4005 001C) bit descriptionBit Symbol Description ResetvalueAccess0 LOCK PLL0 lock indicator 0 R1 FR PLL0 free running indicator 0 R31:2 - Reserved -Table 71. PLL0USB control register (PLL0USB_CTRL, address 0x4005 0020) bit descriptionBit Symbol Value Description ResetvalueAccess0 PD PLL0 power down 1 R/W0 PLL0 enabled1 PLL0 powered down1 BYPASS Input clock bypass control 1 R/W0 CCO clock sent to post-dividers. Use thisin normal operation.1 PLL0 input clock sent to post-dividers(default).2 DIRECTI PLL0 direct input 0 R/W