NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 514 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 514 of 1269NXP Semiconductors UM10503Chapter 23: LPC43xx USB0 Host/Device/OTG controller1 RST Controller reset.Software uses this bit to reset the controller. This bit is set to zero bythe host/device controller when the reset process is complete.Software cannot terminate the reset process early by writing a zero tothis register.R/W 00 This bit is set to zero by hardware when the reset process iscomplete.1 When software writes a one to this bit, the Host Controller resets itsinternal pipelines, timers, counters, state machines etc. to their initialvalue. Any transaction currently in progress on USB is immediatelyterminated. A USB reset is not driven on downstream ports. Softwareshould not set this bit to a one when the HCHalted bit in the USBSTSregister is a zero. Attempting to reset an actively running hostcontroller will result in undefined behavior.2 FS0 Bit 0 of the Frame List Size bits. See Table 401.This field specifies the size of the frame list that controls which bits inthe Frame Index Register should be used for the Frame List Currentindex. Note that this field is made up from USBCMD bits 15, 3, and 2.03 FS1 Bit 1 of the Frame List Size bits. See Table 401. 04 PSE This bit controls whether the host controller skips processing theperiodic schedule.R/W 00 Do not process the periodic schedule.1 Use the PERIODICLISTBASE register to access the periodicschedule.5 ASE This bit controls whether the host controller skips processing theasynchronous schedule.R/W 00 Do not process the asynchronous schedule.1 Use the ASYNCLISTADDR to access the asynchronous schedule.6 IAA This bit is used as a doorbell by software to tell the host controller toissue an interrupt the next time it advances asynchronous schedule.R/W 00 The host controller sets this bit to zero after it has set the Interrupt onSync Advance status bit in the USBSTS register to one.1 Software must write a 1 to this bit to ring the doorbell.When the host controller has evicted all appropriate cached schedulestates, it sets the Interrupt on Async Advance status bit in theUSBSTS register. If the Interrupt on Sync Advance Enable bit in theUSBINTR register is one, then the host controller will assert aninterrupt at the next interrupt threshold.Software should not write a one to this bit when the asynchronousschedule is inactive. Doing so will yield undefined results.7 - - Reserved 09:8 ASP1_0 Asynchronous schedule park modeContains a count of the number of successive transactions the hostcontroller is allowed to execute from a high-speed queue head on theAsynchronous schedule before continuing traversal of theAsynchronous schedule. Valid values are 0x1 to 0x3.Remark: Software must not write 00 to this bit when Park ModeEnable is one as this will result in undefined behavior.R/W 11Table 400. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host modeBit Symbol Value Description Access Resetvalue