NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1011 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1011 of 1269NXP Semiconductors UM10503Chapter 39: LPC43xx SSP0/1Both the SSP and the off-chip serial slave device then clock each data bit into their serialshifter on the falling edge of each CLK. The received data is transferred from the serialshifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.39.7.2 SPI frame formatThe SPI interface is a four-wire interface where the SSEL signal behaves as a slaveselect. The main feature of the SPI format is that the inactive state and phase of the SCKsignal are programmable through the CPOL and CPHA bits within the SSPCR0 controlregister.39.7.2.1 Clock Polarity (CPOL) and Phase (CPHA) controlWhen the CPOL clock polarity control bit is 0, it produces a steady state low value on theSCK pin. If the CPOL clock polarity control bit is 1, a steady state high value is placed onthe CLK pin when data is not being transferred.The CPHA control bit selects the clock edge that captures data and allows it to changestate. It has the most impact on the first bit transmitted by either allowing or not allowing aclock transition before the first data capture edge. When the CPHA phase control bit is 0,data is captured on the first clock edge transition. If the CPHA clock phase control bit is 1,data is captured on the second clock edge transition.39.7.2.2 SPI format with CPOL=0,CPHA=0Single and continuous transmission signal sequences for SPI format with CPOL = 0,CPHA = 0 are shown in Figure 123.a. Single transfer with CPOL=0 and CPHA=0b. Continuous transfer with CPOL=0 and CPHA=0Fig 123. SPI frame format with CPOL=0 and CPHA=0 (a) Single and b) Continuous Transfer)SCKSSELMOSI MSB LSBQMSB LSB4 to 16 bitsMISOSCKSSELMOSIMISO4 to 16 bits 4 to 16 bitsMSB LSBMSB LSBQMSB LSB QMSB LSB