NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 428 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 428 of 1269NXP Semiconductors UM10503Chapter 20: LPC43xx SD/MMC interface20.6.18 Raw Interrupt Status Register (RINTSTS)9 DRTO Data read time-out. Interrupt enabled only if correspondingbit in interrupt mask register is set.010 HTO Data starvation-by-host time-out (HTO). Interrupt enabledonly if corresponding bit in interrupt mask register is set.011 FRUN FIFO underrun/overrun error. Interrupt enabled only ifcorresponding bit in interrupt mask register is set.012 HLE Hardware locked write error. Interrupt enabled only ifcorresponding bit in interrupt mask register is set.013 SBE Start-bit error. Interrupt enabled only if corresponding bit ininterrupt mask register is set.014 ACD Auto command done. Interrupt enabled only ifcorresponding bit in interrupt mask register is set.015 EBE End-bit error (read)/write no CRC. Interrupt enabled only ifcorresponding bit in interrupt mask register is set.016 SDIO_INTERRUPTInterrupt from SDIO card. SDIO interrupt for card enabledonly if corresponding sdio_int_mask bit is set in Interruptmask register (mask bit 1 enables interrupt; 0 masksinterrupt).0 - No SDIO interrupt from card1 - SDIO interrupt from cardIn MMC-Ver3.3-only mode, this bit is always 0.-31:17 - Reserved -Table 313. Masked Interrupt Status Register (MINTSTS, address 0x4000 4040) bit descriptionBit Symbol Description ResetvalueTable 314. Raw Interrupt Status Register (RINTSTS, address 0x4000 4044) bit descriptionBit Symbol Description Resetvalue0 CDET Card detect. Writes to bits clear status bit. Value of 1 clearsstatus bit, and value of 0 leaves bit intact. Bits are loggedregardless of interrupt mask status.01 RE Response error. Writes to bits clear status bit. Value of 1clears status bit, and value of 0 leaves bit intact. Bits arelogged regardless of interrupt mask status.02 CDONE Command done. Writes to bits clear status bit. Value of 1clears status bit, and value of 0 leaves bit intact. Bits arelogged regardless of interrupt mask status.03 DTO Data transfer over. Writes to bits clear status bit. Value of 1clears status bit, and value of 0 leaves bit intact. Bits arelogged regardless of interrupt mask status.04 TXDR Transmit FIFO data request. Writes to bits clear status bit.Value of 1 clears status bit, and value of 0 leaves bit intact.Bits are logged regardless of interrupt mask status.05 RXDR Receive FIFO data request. Writes to bits clear status bit.Value of 1 clears status bit, and value of 0 leaves bit intact.Bits are logged regardless of interrupt mask status.0