NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 362 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 362 of 1269NXP Semiconductors UM10503Chapter 18: LPC43xx Serial GPIO (SGPIO)18.6.16 Slice count enable register (CTRL_ENABLED)18.6.17 Slice count disable register (CTRL_DISABLED)When this register is set, it synchronously disables the POSi counter when the POSicounter reaches a zero count. The CTRL_DISABLED register is not cleared at that time: itremains set.When starting COUNTi (by setting CTRL_ENABLEi), this register should always becleared. If only on POSi countdown is needed (when only one slice should be processed),then this register should be set after COUNTi is started with register CTRL_ENABLEi.18.6.18 Shift clock interrupt clear mask register (CLR_EN_0)This register clears the shift clock interrupt mask of a slice.18.6.19 Shift clock interrupt set mask register (SET_EN_0)This register masks the shift clock interrupt of a slice.Table 230. Slice count enable register (CTRL_ENABLED, address 0x4010 121C) bitdescriptionBit Symbol Description ResetvalueAccess15:0 CTRL_ENABLED Slice count enable. Bit n controls slice n (0 = sliceA, ..., 15 = slice P).0 = .1 = Enables COUNTn.0 R/W31:16 - Reserved. - -Table 231. Slice count disable register (CTRL_DISABLED, address 0x4010 1220) bitdescriptionBit Symbol Description ResetvalueAccess15:0 CTRL_DISABLED Slice count disable. Bit n controls slice n, (0 =slice A, ..., 15 = slice P).1 = Disables POS counter of slice n.0 R/W31:16 - Reserved. - -Table 232. Shift clock interrupt clear mask register (CLR_EN_0, address 0x4010 1F00) bitdescriptionBit Symbol Description ResetvalueAccess15:0 CLR_SCI 1 = Shift clock interrupt clear mask of slice n. 0 W31:16 - Reserved. - -Table 233. Shift clock interrupt set mask register (SET_EN_0, address 0x4010 1F04) bitdescriptionBit Symbol Description ResetvalueAccess15:0 SET_SCI 1 = Shift clock interrupt set mask of slice n. 0 W31:16 - Reserved. - -