NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 128 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 128 of 1269NXP Semiconductors UM10503Chapter 11: LPC43xx Clock Generation Unit (CGU)• mode 1a: Normal operating mode without post-divider and without pre-divider• mode 1b: Normal operating mode with post-divider and without pre-divider• mode 1c: Normal operating mode without post-divider and with pre-divider• mode 1d: Normal operating mode with post-divider and with pre-dividerTo get at the output of the PLL (clkout) the best phase-noise and jitter performance, thehighest possible reference clock (clkref) at the PFD has to be used. Therefore mode 1aand 1b are recommended, when it is possible to make the right output frequency withoutpre-divider.By using the post-divider the clock at the output of the PLL (clkout) the divider ratio isalways even because the divide-by-2 divider after the post-divider.11.7.4.3.2 Mode 1a: Normal operating mode without post-divider and without pre-dividerIn normal operating mode 1a the post-divider and pre-divider are bypassed. The operatingfrequencies are:Fout = Fcco = 2 x M x Fin (275 MHz Fcco 550 MHz, 4 kHz  Fin 150 MHz)The feedback divider ratio is programmable:• Feedback-divider M (M, 1 to 2 15)11.7.4.3.3 Mode 1b: Normal operating mode with post-divider and without pre-dividerIn normal operating mode 1b the pre-divider is bypassed. The operating frequencies are:Fout = Fcco /(2 x P) = (M / P) x Fin  (275 MHz Fcco 550 MHz, 4 kHz Fin  150 MHz)The divider ratios are programmable:• Feedback-divider M (M, 1 to 2 15)• Post-divider P (P, 1 to 32)11.7.4.3.4 Mode 1c: Normal operating mode without post-divider and with pre-dividerIn normal operating mode 1c the post-divider with divide-by-2 divider is bypassed. Theoperating frequencies are:Fout = Fcco = 2 x M x Fin / N  (275 MHz Fcco 550 MHz, 4 kHz Fin/N 150 MHz)The divider ratios are programmable:• Pre-divider N (N, 1 to 256)• Feedback-divider M (M, 1 to 2 15)Table 93. DIRECTL and DIRECTO bit settings in HP0/1_Mode registerMode DIRECTI DIRECTO1a 1 11b 1 01c 0 11d 0 0