NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 914 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 914 of 1269NXP Semiconductors UM10503Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT)32.6 RI timer operationFollowing reset, the counter begins counting up from 0x0000 0000. Whenever the countervalue equals the value programmed into the COMPVAL register the interrupt flag will beset. Any bit or combination of bits can be removed from this comparison (i.e. forced tocompare) by writing a ‘1’ to the corresponding bit(s) in the MASK register. If the enable_clrbit is low (default state), a valid comparison ONLY causes the interrupt flag to be set. Ithas no effect on the count sequence. Counting continues as usual. When the counterreaches 0xFFFFFFFF it rolls-over to 0x000 00000 on the next clock and continuescounting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter tobe reset to zero. Counting will resume from there on the next clock edge.Counting can be halted in software by writing a ‘0’ to the RITEN bit. Counting will also behalted when the processor is halted for debugging provided the RITENBR bit is set. Boththe RITEN and RITENBR bits are set on reset.The interrupt flag can be cleared in software by writing a ‘1’ to the RITINT bit.Software can load the counter to any value at any time by writing to COUNTER.The counter (COUNTER), COMPVAL register, MASK register and CTRL register can allbe read by software at any time.