NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1036 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1036 of 1269NXP Semiconductors UM10503Chapter 41: LPC43xx I2S interface41.6.2 I2S Digital Audio Input registerThe DAI register controls the operation of the I2S receive channel. The function of bits inDAI are shown in Table 899.41.6.3 I2S Transmit FIFO registerThe TXFIFO register provides access to the transmit FIFO.41.6.4 Receive FIFO registerThe I2SRXFIFO register provides access to the receive FIFO.3 STOP When 1, disables accesses on FIFOs, places the transmit channel in mutemode.04 RESET When 1, asynchronously resets the transmit channel and FIFO. 05 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slavemode.114:6 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F15 MUTE When 1, the transmit channel sends only zeroes. 131:16 - Reserved, user software should not write ones to reserved bits. The value readfrom a reserved bit is not defined.-Table 898. I2S Digital Audio Output register (DAO - address 0x400A 2000 (I2S0) and 0x400A 3000 (I2S1)) bitdescriptionBit Symbol Value Description ResetvalueTable 899. I2S Digital Audio Input register (DAI - address 0x400A 2004 (I2S0) and 0x400A 3004 (I2S1)) bit descriptionBit Symbol ValueDescription Resetvalue1:0 WORDWIDTH Selects the number of bytes in data as follows: 010x0 8-bit data0x1 16-bit data0x2 Reserved, do not use this setting0x3 32-bit data2 MONO When 1, data is of monaural format. When 0, the data is in stereo format. 03 STOP When 1, disables accesses on FIFOs, places the transmit channel in mutemode.04 RESET When 1, asynchronously reset the transmit channel and FIFO. 05 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slavemode.114:6 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F31:15 - Reserved, user software should not write ones to reserved bits. The valueread from a reserved bit is not defined.-Table 900. Transmit FIFO register (TXFIFO - address 0x400A 2008 (I2S0) and 0x400A 3008 (I2S1)) bit descriptionBit Symbol Description Reset value31:0 I2STXFIFO 8 x 32-bit transmit FIFO. 0