NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 1114 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1114 of 1269NXP Semiconductors UM10503Chapter 43: LPC43xx I2C-bus interfaceWhen STA is 1 and the I2C interface is not already in master mode, it enters master mode,checks the bus and generates a START condition if the bus is free. If the bus is not free, itwaits for a STOP condition (which will free the bus) and generates a START conditionafter a delay of a half clock period of the internal clock generator. If the I2 C interface isalready in master mode and data has been transmitted or received, it transmits aRepeated START condition. STA may be set at any time, including when the I 2 C interfaceis in an addressed slave mode.STA can be cleared by writing 1 to the STAC bit in the CONCLR register. When STA is 0,no START condition or Repeated START condition will be generated.If STA and STO are both set, then a STOP condition is transmitted on the I2C-bus if it theinterface is in master mode, and transmits a START condition thereafter. If the I2Cinterface is in slave mode, an internal STOP condition is generated, but is not transmittedon the bus.STO is the STOP flag. Setting this bit causes the I 2C interface to transmit a STOPcondition in master mode, or recover from an error condition in slave mode. When STO is1 in master mode, a STOP condition is transmitted on the I2 C-bus. When the bus detectsthe STOP condition, STO is cleared automatically.In slave mode, setting this bit can recover from an error condition. In this case, no STOPcondition is transmitted to the bus. The hardware behaves as if a STOP condition hasbeen received and it switches to “not addressed” slave receiver mode. The STO flag iscleared by hardware automatically.SI is the I2C Interrupt Flag. This bit is set when the I 2 C state changes. However, enteringstate F8 does not set SI since there is nothing for an interrupt service routine to do in thatcase.While SI is set, the low period of the serial clock on the SCL line is stretched, and theserial transfer is suspended. When SCL is HIGH, it is unaffected by the state of the SI flag.SI must be reset by software, by writing a 1 to the SIC bit in CONCLR register.AA is the Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA)will be returned during the acknowledge clock pulse on the SCL line on the followingsituations:1. The address in the Slave Address Register has been received.2. The General Call address has been received while the General Call bit (GC) in ADR isset.3. A data byte has been received while the I2C is in the master receiver mode.4. A data byte has been received while the I2C is in the addressed slave receiver modeThe AA bit can be cleared by writing 1 to the AAC bit in the CONCLR register. When AA is0, a not acknowledge (HIGH level to SDA) will be returned during the acknowledge clockpulse on the SCL line on the following situations:1. A data byte has been received while the I2C is in the master receiver mode.2. A data byte has been received while the I2C is in the addressed slave receiver mode.